Abstract: A method of manufacturing a photomask includes at least the following steps. First, a phase shift layer and a hard mask layer are formed on a light transmitting substrate. A predetermined mask pattern is split into a first pattern and a second pattern. A series of processes is performed so that the hard mask layer and the phase shift layer have the first pattern and the second pattern. The series of processes includes at least the following steps. First, a first exposure process for transferring the first pattern is performed. Thereafter, a second exposure process for transferring the second pattern is performed. The first exposure process and the second exposure process are executed by different machines.

Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.

Abstract: A method of controlling a position of an adjustable nozzle includes depositing a film on a surface of a wafer. The method includes measuring a thickness profile of the surface of the wafer. The method includes comparing the measurement of the thickness profile with a reference value using a control unit. The method includes transmitting a control signal to the adjustable nozzle to alter the position of the adjustable nozzle based on the result of the comparison. The adjustable nozzle includes a base having a hollow center portion for conducting gas, the base configured for connection to a gas source. The adjust nozzle includes a tip coupled to the base and having an opening for conducting gas from the base to the exterior of the nozzle, wherein the base is configured for pivoting about a longitudinal axis of the base in response to the control signal.

Abstract: Systems, methods, and devices are described herein for a deterministic approach that includes receiving an original layout of a semiconductor device that has a number of layers. A violation of a first design rule associated with a first layer of the number of layers is identified. A design rule compilation includes a plurality of design rules associated with each layer of the number of layers. A plurality of derived layers are generated based upon the plurality of design rules. Each derived layer of the plurality of derived layers includes one or more layers of the number of layers of the semiconductor device in which a physical movement to one layer impacts another layer. A forbidden region associated with a second layer of the plurality of layers is designated. A new layout of the number of layers having oriented differently than the original layout is generated such that no layer protrudes within the forbidden region.

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first transistor formed in a first region of the semiconductor device. The first transistor includes a first channel structure extending between a source terminal and a drain terminal of the first transistor. The first transistor includes a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device. Further, the first transistor includes a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.

Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A method for increasing coverage of a scan test, executed by at least one processor, includes following operations: analyzing a first netlist file and a second netlist file to acquire a change of a circuit structure, in which the first netlist file corresponds to a first scan chain circuitry, and the second netlist file corresponds to a second scan circuitry wherein the second netlist file is generated by processing the first netlist file with executing an engineering change order (ECO); repairing the second scan chain circuitry according to at least one predetermined criterion; evaluating a candidate node of the repaired second scan chain circuitry, to connect a new flip flop circuit generated after executing the ECO to the candidate node; and storing the second netlist file being processed as a third netlist file, to fabricate an integrated circuit.

Abstract: A wafer structure, a method for manufacturing the wafer structure, and a chip structure. A front surface of a first chip provided with a photosensitive array is bonded to a front surface of a second chip provided with a logic device. An electrical-connection through-hole is provided on a back surface of the first chip at a pad region. The electrical-connection through-hole runs from the back surface of the first chip, via a top wiring layer in the first chip, to a top wiring layer in the second chip. A pad is provided on the electrical-connection through-hole. Hence, integration of a photosensitive device of a stacked type is achieved. There are advantages of a high integration degree and a simple structure. Transmission efficiency of a device is effectively improved, and complexity of a manufacturing process is reduced.

Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.

Abstract: A method includes switching a receiver path network of a front-end module to a first matching mode in a receive mode. The method further includes switching a transmitter path network of the front-end module to a first resonance mode in the receive mode. The method further includes switching the transmitter path network to a second matching mode in a transmit mode. The method further includes switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A semiconductor device includes a first source/drain structure, a channel layer, a second source/drain structure, a gate structure and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on opposite first and second sidewalls of the channel layer when viewed in a first cross-section taken along a first direction. The gate structure is also on a third sidewall of the channel layer but absent from a fourth sidewall of the channel layer when viewed in a second cross-section taken along a second direction different from the first direction. The epitaxial layer is on the fourth sidewall of the channel layer when viewed in the second cross-section and forming a P-N junction with the channel layer.

Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors.

Abstract: Provided are MIM capacitor and semiconductor structure including MIM capacitor. The MIM capacitor includes a dielectric structure, a bottom electrode on the dielectric structure, a first insulating layer covering the bottom electrode and the dielectric structure, a middle electrode stacked on the bottom electrode, a spacer, a second insulating layer and a top electrode. The middle electrode is separate from the bottom electrode by the first insulating layer therebetween. A bottommost surface of the middle electrode is lower than a top surface of the bottom electrode and higher than a bottom surface of the bottom electrode. The spacer is disposed on the first insulating layer and laterally aside and covers a sidewall of the middle electrode. The second insulating layer covers the middle electrode and the spacer. The top electrode is stacked on the middle electrode and separate from the middle electrode by the second insulating layer therebetween.

Abstract: A semiconductor device includes a semiconductor substrate, a photo sensing region, and a plurality of nanostructures. The semiconductor substrate has a first dopant. The photo sensing region is embedded in the semiconductor substrate, has a top surface level with a top surface of the semiconductor substrate, and has a second dopant that is of a different conductivity type than the first dopant. The plurality of nanostructures is on the photo sensing region and is made of a material the same as the photo sensing region.