Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Abstract: An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core. The at least one tightly coupled smart memory unit includes a memory unit, and a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit.

Abstract: Semiconductor devices and methods of epitaxially forming a semiconductor layer in a recess of a semiconductor device are disclosed. In some embodiments, a method of epitaxially forming a semiconductor layer in a recess may include: providing a chemical vapor deposition system; placing a semiconductor substrate having a recess into the chemical vapor deposition system, wherein the semiconductor substrate includes at least one fissure extending from a surface of the recess into the semiconductor substrate; epitaxially forming a liner including a first semiconductor material within the recess and over the at least one fissure; and epitaxially forming a semiconductor layer including a second semiconductor material over the liner.

Abstract: A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

Abstract: A method and apparatus for alignment are disclosed. An exemplary apparatus includes an overlay mark formed on a substrate; and a plurality of dummy features formed nearby the overlay mark. The dummy features have dimensions below a minimum resolution of an alignment detection tool. A minimum distance separating the overlay mark from its closest dummy feature is correlated to a semiconductor fabrication technology generation under which the overlay mark is formed.

Abstract: A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract: A probe card for wafer level test includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes a first surface having a first pitch and a second surface having a second pitch substantially less than the first pitch, a printed circuit board configured approximate the first surface of the space transformer, a first power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line to the printed circuit board, and a second power plane disposed on a surface of the printed circuit board and patterned to couple the power line and the ground line of the space transformer to the printed circuit board, wherein the second power plane is in electrical connection with the first power plane.

Abstract: A rectangular helix antenna in an integrated circuit includes upper electrodes disposed in a first metal layer, lower electrodes disposed in a second metal layer, and side electrodes connecting the upper electrodes with the lower electrodes, respectively. The upper electrodes are disposed at an angle with respect to the lower electrodes. The upper electrodes, the lower electrodes, and the side electrodes form one continuous electrode spiraling around an inner shape of a rectangular bar. A micro-electromechanical system (MEMS) helix antenna has a similar structure to the rectangular helix antenna, but can have an inner shape of a bar.

Abstract: Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls.

Abstract: A semiconductor structure includes a substrate and first and second crystalline semiconductor layers. The first crystalline semiconductor layer has a first crystal orientation, and includes a crystallized amorphous region formed on the substrate. The second crystalline semiconductor layer is formed on the substrate, is laterally disposed of the first crystalline semiconductor layer, and has a second crystal orientation different from the first crystal orientation. A method of fabricating the semiconductor structure is also disclosed.

Abstract: A MEMS capacitive pressure sensor is provided. The MEMS capacitive pressure sensor includes a substrate having a first region and a second region, and a first dielectric layer formed on the substrate. The capacitive pressure sensor also includes a second dielectric layer having a step surface profile formed on the first dielectric layer, and a first electrode layer having a step surface profile formed on the second dielectric layer. Further, the MEMS capacitive pressure sensor includes an insulation layer formed on the first electrode layer, and a second electrode layer having a step surface profile with a portion formed on the insulation layer in the peripheral region and the rest suspended over the first electrode layer in the device region. Further, the MEMS capacitive pressure sensor also includes a chamber having a step surface profile formed between the first electrode layer and the second electrode layer.

Abstract: A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

Abstract: A method of forming a semiconductor die comprises covering a first subset of a plurality of dummy gate electrodes and a second subset of the plurality of dummy gate electrodes with a first mask layer, the mask layer being patterned to expose a third subset of the plurality of dummy gate electrodes. The method also comprises removing the third subset of the plurality of dummy gate electrodes to form a first set of openings. The method further comprises filling the first set of openings with a first metal material to form a plurality of P-metal gate areas covering a first area of the major surface within a first device region over the major surface and to form a plurality of dummy P-metal gate areas collectively covering a second area of the major surface within a second device region over the major surface.

Abstract: A capacitive pressure sensor is provided. The capacitive pressure sensor includes a substrate; and a first electrode formed in one surface of the substrate and vertical to the surface of the substrate. The capacitive pressure sensor also includes a second electrode with a portion facing the first sub-electrode, a portion facing the second sub-electrode and a portion formed in the other surface of the substrate. Further, the capacitive pressure sensor includes a first chamber between the first electrode and the second electrode and a second chamber formed in the second electrode. Further, the pressure sensor also includes a first sealing layer formed on the second electrode; and a second sealing layer formed on the other surface of the substrate.

Abstract: The invention relates to an isolation structure of a semiconductor device. An exemplary isolation structure for a semiconductor device comprises a substrate comprising a trench; a strained material in the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an oxide layer of the strained material over the strained material; a high-k dielectric layer over the oxide layer; and a dielectric layer over the high-k dielectric layer filling the trench.

Abstract: A circuit comprises a first layer comprising a first voltage line, a first transistor coupled with the first voltage line, a second transistor coupled with the first voltage line, and a first line coupling a drain of the first transistor with a gate of the second transistor. The circuit also comprises a second layer comprising a second voltage line, a third transistor coupled with the second voltage line, a fourth transistor coupled with the second voltage line, and a second line coupling a drain of the third transistor with a gate of the fourth transistor. The circuit further comprises an inter-layer interconnect structure coupling the first transistor with the third transistor, and the second transistor with the fourth transistor.

Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.

Abstract: A uni-terminal transistor device is described. In one embodiment, an n-channel transistor comprises a first semiconductor layer having a discrete hole level H0; a second semiconductor layer having a conduction band minimum EC2; a wide bandgap semiconductor barrier layer disposed between the first and the second semiconductor layers; a gate dielectric layer disposed above the first semiconductor layer; and a gate metal layer disposed above the gate dielectric layer and having an effective workfunction selected to position the discrete hole level H0 below the conduction band minimum Ec2 for zero bias applied to the gate metal layer and to obtain n-terminal characteristics.