Patents Assigned to Semiconductor Research Foundation
  • Patent number: 4641167
    Abstract: A semiconductor optoelectro transducer is highly sensitive in infrared to far infrared regions and is operable at high speed. To this end, the optoelectro transducer is formed by a static induction transistor or a static induction thyristor and an element which are excited by light of longer wavelength than that of light corresponding to the energy of the energy gap of a channel region, is added to the channel region which receives light.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: February 3, 1987
    Assignee: Semiconductor Research Foundation
    Inventor: Jun-chi Nishizawa
  • Patent number: 4629901
    Abstract: The present invention has for its object to provide a photo coupler which is operable with high sensitivity, high speed, low voltage and small current. To this end, a photo detector (13, 20, 33), which is coupled with one light emitting element (11, 21, 31) through a light transparent insulator, is formed by any one of a static induction transistor, field effect transistor and a static induction transistor.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: December 16, 1986
    Assignee: Semiconductor Research Foundation
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4608587
    Abstract: The present invention has for its object to make a semiconductor optoelectro transducer higher-speed and higher-sensitivity. To this end, a field effect transistor, static induction transistor or static induction thyristor is used as a basic element and at least one portion of the gate region is exposed at the wafer surface.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: August 26, 1986
    Assignee: "Semiconductor Research Foundation"
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4540466
    Abstract: Photochemical technique is applied, in a unique manner, to the so-called dry process intended for etching a substrate or for deposition thereon in the presence of a gas supplied into a chamber containing the substrate. The interior of this chamber is so structured as to produce a higher pressure gas region and a lower pressure gas region. A beam of light rays is caused to impinge onto the former region to activate the particles of gas. The resulting gas containing the activated particles is fed onto the substrate placed in the latter region as carried through at least one passageway provided between the two regions by the flow of gas caused due to the difference in pressure of gas in these two regions. Thus, the aimed etching or deposition is carried out without damaging the surface of the substrate which would occur by the collision of the otherwise heavily energized particles against the surface of the substrate.
    Type: Grant
    Filed: April 26, 1984
    Date of Patent: September 10, 1985
    Assignee: Semiconductor Research Foundation
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4506281
    Abstract: This invention relates to a GaAs semiconductor device and more particularly to a GaAs static induction transistor integrated circuit which operates at a very high speed. Gallium arsenide has the features that the mobility of electrons is higher than that in silicon and that the band structure has a direct gap. The mobility of electrons in gallium arsenide is several times as high as that in silicon; this is very suitable for the manufacture of a semiconductor device of high-speed operation. Further, since gallium arsenide has the direct gap, the electron-hole recombination rate is high and the minority carrier storage effect is extremely small. By causing the recombination at the direct gap, light emission can be achieved more efficiently. Accordingly, a light receiving and emitting semiconductor device can be obtained through the use of gallium arsenide. As the propagation velocity of light is very fast, signal transfer between semiconductor chips can be achieved at ultra-high speed.
    Type: Grant
    Filed: August 24, 1981
    Date of Patent: March 19, 1985
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 4504865
    Abstract: From each of a plurality of picture element cells having a non-destructive readout characteristic, arranged two-dimensionally and connected to the same signal output line, an image signal is read out without mutual interference of the picture elements. To this end, a blanking period is provided between the readout periods of the respective picture element cells connected to the same signal output line and, in this blanking period, the signal output line is cleared (refreshed).
    Type: Grant
    Filed: September 16, 1982
    Date of Patent: March 12, 1985
    Assignees: Semiconductor Research Foundation, Fuji Photo Film Co., Ltd.
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi, Makoto Murakoshi, Koji Shimanuki
  • Patent number: 4479845
    Abstract: In vapor growth of a doped semiconductor layer on a substrate, a plurality of sampling points are selected in the layer to be grown and in the substrate and each treated as a diffusion source. Computation is carried out to provide the actual doping program for realizing a desired doping profile and to provide the resultant doping profile from the actual doping characteristics. Monitoring means monitors the vapor growth and feeds back information to computing means. The computing means rearrange the doping program and supply command to means for controlling the vapor growth.It is found it is effective to invert the conductivity type of impurity at least two times particularly in the initial stage of the vapor growth for providing a sharp profile of net impurity distribution.
    Type: Grant
    Filed: June 14, 1982
    Date of Patent: October 30, 1984
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nisizawa, Masaaki Fukase
  • Patent number: 4454526
    Abstract: A semiconductor image sensor of wide dynamic range, high sensitivity, low noise and high image clarity, which is provided with a hook structure for detecting radiant energy input information, a readout transistor and means for refreshing stored optical information and which is capable of non-destructive readout of optical information, and a method of operating such a semiconductor image sensor. The impurity concentrations in the hook structure, their distribution profiles, materials of layers forming the hook structure and their thicknesses are so selected as to optimize the carrier storage function of the hook structure, thereby permitting the non-destructive readout of the optical information. The ratio between the junction capacitance and the earth capacitance of a floating pn junction establishing a potential barrier in the hook structure is selected so that a stored voltage in the floating pn junction and the readout sensitivity may become maximum.
    Type: Grant
    Filed: May 20, 1981
    Date of Patent: June 12, 1984
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi, Takashige Tamamushi
  • Patent number: 4448525
    Abstract: A crystal defect analyzer comprises acousto-electric transducer means disposed in close adherence to a sample to be analyzed through the medium of a filter layer which functions to intercept light or electrons or particles emitted from said excitation means and to transmit only acoustic waves produced within said sample by excitation, thereby it can attain higher response and sensitivity, smaller size, higher resistance to vibration and superior operationality.
    Type: Grant
    Filed: June 26, 1981
    Date of Patent: May 15, 1984
    Assignee: Semiconductor Research Foundation
    Inventors: Nobuo Mikoshiba, Kazuo Tsubouchi, Kenji Wasa
  • Patent number: 4408304
    Abstract: A semiconductor memory is provided with a hook structure composed of first to fourth regions and is capable of non-destructive readout. The third and fourth regions of the hook structure are both made floating and each form one of main electrode regions of each of a write and/or refresh transistor and a readout transistor. Carriers which are injected from the other main electrode region of the write transistor are stored as excess majority carriers in the third region and majority carriers of the fourth region flow out therefrom into the first region via the third and second regions, in consequence of which the fourth region lacks in the majority carrier and voltages of the floating third and fourth regions vary. The voltage variation of the fourth region is read out by the readout transistor. The excess majority carriers stored in the third region flow out therefrom into the other main electrode region of the write transistor and become extinct when it operates as a refresh transistor.
    Type: Grant
    Filed: May 4, 1981
    Date of Patent: October 4, 1983
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Ohmi Tadahiro, Takashige Tamamushi
  • Patent number: 4377817
    Abstract: This invention relates to a semiconductor image sensors and more particularly, to a back-illuminated-type static induction transistor image sensors.FIGS. 4A to 4C show the back illuminated type SIT image sensors operating in the electron depletion storing mode, where the n.sup.+ buried floating region 23 serves as storage region.
    Type: Grant
    Filed: March 17, 1980
    Date of Patent: March 22, 1983
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 4333989
    Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consisting essentially of sapphire (aluminum oxide) and at least one additive selected from a group consisting of oxides of gallium. A 87 mol percent content of gallium oxide is most preferred for a silicon layer. Similarly, an additive and its content should most preferably be selected depending on the semiconductor, which may be gallium phosphide, aluminium phosphide, or zinc sulphide.
    Type: Grant
    Filed: February 22, 1982
    Date of Patent: June 8, 1982
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-Ichi Nishizawa, Kitsuhiro Kimura
  • Patent number: 4320410
    Abstract: This invention relates to a GaAs semiconductor device and more particularly to a GaAs static induction transistor integrated circuit which operates at a very high speed. Gallium arsenide has the features that the mobility of electrons is higher than that in silicon and that the band structure has a direct gap. The mobility of electrons in gallium arsenide is several times as high as that in silicon; this is very suitable for the manufacture of a semiconductor device of high-speed operation. Further, since gallium arsenide has the direct gap, the electron-hole recombination rate is high and the minority carrier storage effect is extremely small. By causing the recombination at the direct gap, light emission can be achieved more efficiently. Accordingly, a light receiving and emitting semiconductor device can be obtained through the use of gallium arsenide. As the propagation velocity of light is very fast, signal transfer between semiconductor chips can be achieved at ultra-high speed.
    Type: Grant
    Filed: May 3, 1979
    Date of Patent: March 16, 1982
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 4297718
    Abstract: Vertical type field effect transistors are disclosed including one of the highly doped source, gate and drain regions disposed on one of the main opposite faces of one of the semiconductor substrate and the remaining region or regions disposed on the other mainface of the substrate. At least one of the regions is divided into a plurality of elongated slender portions and metallic electrodes are disposed in ohmic contact with the respective regions so as to be identical in configuration to the latter. The highly doped regions themselves may form electrodes.
    Type: Grant
    Filed: June 8, 1976
    Date of Patent: October 27, 1981
    Assignee: Semiconductor Research Foundation Mitsubishi Denki K.K.
    Inventors: Jun-Ichi Nishizawa, Takashi Kitsuregawa
  • Patent number: 4292373
    Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consists essentially of sapphire (aluminum oxide) and magnesium titanium oxide (MgTiO.sub.3). The invention also provides the aforesaid single crystal substrate in combination with a semiconductor epitaxially grown thereon. The preferred semiconductors are silicon, gallium phosphide, aluminum phosphide and zinc sulphide.
    Type: Grant
    Filed: May 19, 1980
    Date of Patent: September 29, 1981
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Mitsuhiro Kimura
  • Patent number: 4292374
    Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consists essentially of sapphire (aluminum oxide) and scandium oxide (Sc.sub.2 O.sub.3). The invention also provides the aforesaid single crystal substrate in combination with a semiconductor epitaxially grown thereon. The preferred semiconductors are silicon, gallium phosphide, aluminum phosphide and zinc sulphide.
    Type: Grant
    Filed: May 19, 1980
    Date of Patent: September 29, 1981
    Assignee: Semiconductor Research Foundation
    Inventors: Jun-ichi Nishizawa, Mitsuhiro Kimura
  • Patent number: 4198645
    Abstract: A semiconductor controlled rectifier comprises a semiconductor substrate consisting of a first layer having a first conductivity type, a second layer having a second conductivity type and disposed adjacent to the first layer, and a plurality of base regions having the first conductivity type and a higher impurity concentration than the second layer and disposed at predetermined distances from one another within the second layer in at least one direction; a pair of electrodes are kept respectively in contact with the surfaces of the first and the second layer; and a control electrode is kept in contact with the respective base regions.
    Type: Grant
    Filed: April 27, 1978
    Date of Patent: April 15, 1980
    Assignee: Semiconductor Research Foundation
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4177321
    Abstract: A grown crystal structure comprises a single crystal of semiconductive material having a given lattice constant grown on a spinel crystal substrate having a different lattice constant. A substance is added to one or both of the crystals and has suitable properties relative to the crystals to effectively reduce lattice strains developed in the grown crystal structure due to mismatch of the lattice constants of both crystals.
    Type: Grant
    Filed: May 18, 1978
    Date of Patent: December 4, 1979
    Assignee: Semiconductor Research Foundation
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4171995
    Abstract: A process of manufacturing a static induction thyristor comprising providing a semiconductor substrate of the first conductivity type which defines a first semiconductor layer and forming a second semiconductor layer thereon of a second conductivity type. The first and second semiconductor layers have relative impurity concentrations effective for forming therebetween charge depletion regions when no electrical signal is applied to the second semiconductor layer and which prevent injection of charge carriers through the second semiconductor layer when the thyristor is in a blocking state, and such that electrically forward biasing the second semiconductor layer effectuates a sufficient reduction of the depletion regions that a sufficient quantity of charge carriers may be injected through the second semiconductor layer that the thryistor switches to a conductive state. The second semiconductor layer defines the gate region of the thyristor.
    Type: Grant
    Filed: January 18, 1977
    Date of Patent: October 23, 1979
    Assignees: Semiconductor Research Foundation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Jun-ichi Nishizawa, Kentaro Nakamura, Takashi Kitsuregawa
  • Patent number: 4126731
    Abstract: A single crystal substrate for epitaxial growth thereon of a semiconductor layer. The substrate consisting essentially of sapphire (aluminium oxide) and at least one additive selected from a group consisting of oxides of gallium, titanium, scandium, and others. A 87 mol percent content of gallium oxide is most preferred for a silicon layer. Similarly, an additive and its content should most preferably be selected depending on the semiconductor, which may be gallium phosphide, aluminium phosphide, or zinc sulphide.
    Type: Grant
    Filed: October 24, 1975
    Date of Patent: November 21, 1978
    Assignees: Semiconductor Research Foundation, Tohoku Metal Industries Limited
    Inventors: Jun-ichi Nishizawa, Mitsuhiro Kimura