Patents Assigned to Semiconductor Technologies & Instruments, Inc.
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Patent number: 6765666Abstract: A system for inspecting a component, such as a die formed on a silicon wafer, is provided. The system includes a two dimensional inspection system that can locate one or more features, such as bump contacts on the die, and which can also generate feature coordinate data. The system also includes a three dimensional inspection system that is connected to the two dimensional inspection system, such as through an operating system of a processor. The three dimensional inspection system receives the feature coordinate data and generates inspection control data.Type: GrantFiled: August 3, 2000Date of Patent: July 20, 2004Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Clyde Maxwell Guest, Younes Chtioui, Rajiv Roy, Charles K. Harris, Weerakiat Wahawisan, Thomas C. Carrington
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Patent number: 6744913Abstract: A system for locating features in image data is provided. The system includes a first component system. The first component system compares first component data, which can be pixel data of a first user-selected component of the feature, to first test image data, which can be selected by scanning image data of a device, such as a die cut from a silicon wafer. The system also includes second component system that is connected to the first component system, such as through data memory locations of a processor. The second component system compares second component data to second test image data if the first component system finds a match between the first component data and the first test image data. The second test image data is selected based upon the first test image data, such as by using a known coordinate relationship between pixels of the first component data and the second component data.Type: GrantFiled: April 18, 2000Date of Patent: June 1, 2004Assignee: Semiconductor Technology & Instruments, Inc.Inventors: Clyde Maxwell Guest, John Mark Thornell
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Patent number: 6459807Abstract: A system for processing image data, such as an image of a die cut from a silicon wafer, is provided. The system includes an irregular edge detection system, which can locate edge data of a feature of the image data, such as the edge of a probe mark in a bond pad. A feature area calculation system is connected to the irregular edge detection system, such as by accessing data stored by the irregular edge detection system. The feature area calculation system can receive the edge data of the feature and determining the area of the feature, such as by summing normalized pixel area values. The irregular edge detection system uses interpolation to locate edges that occur between the centerpoints of adjacent pixels.Type: GrantFiled: June 13, 2000Date of Patent: October 1, 2002Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Clyde Maxwell Guest, Chu-Yin Chang
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Patent number: 6445518Abstract: A semiconductor device lead inspection apparatus and method are provided for capturing images of the semiconductor edges and leads along two optical axes which have different directions in a plane perpendicular to the semiconductor device edge. A first image is reflected off an optical surface of a prism to a direction corresponding to the camera optical axis. A second image is reflected by two optical surfaces of the prism to a direction corresponding to the camera optical axis.Type: GrantFiled: November 28, 2000Date of Patent: September 3, 2002Assignee: Semiconductor Technologies & Instruments, Inc.Inventor: Pao Meng Lee
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Patent number: 6396578Abstract: A system for inspection components that are sealed within tape is provided. The system includes a light source that can illuminate the components through a tape layer. A polarizer is used to polarize light from the light source, the components, and the tape layer, so as to reduce glare and reflected light. An image system receives light from the polarizer and stores image data for each component.Type: GrantFiled: March 21, 2001Date of Patent: May 28, 2002Assignee: Semiconductor Technologies & Instruments, Inc.Inventor: Tay Bok Her
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Patent number: 6259522Abstract: A system for inspection components that are sealed within tape is provided. The system includes a light source that can illuminate the components through a tape layer. A polarizer is used to polarize light from the light source, the components, and the tape layer, so as to reduce glare and reflected light. An image system receives light from the polarizer and stores image data for each component.Type: GrantFiled: October 29, 1999Date of Patent: July 10, 2001Assignee: Semiconductor Technologies & Instruments, Inc.Inventor: Tay Bok Her
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Patent number: 6252981Abstract: A system for selecting reference die images, such as for use with a visual die inspection system, is provided. The system includes a die image comparator, which compares a first die image to a second die image in order to create a difference image that contains only the differences between the two die images. The system also includes a difference image analysis system that receives data from the die image comparator. The difference image analysis system analyzes the difference image and determines whether there are any features of the difference image that indicate that either the first die image or the second die image should not be used as a reference die image.Type: GrantFiled: March 17, 1999Date of Patent: June 26, 2001Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Clyde Maxwell Guest, Rajiv Roy, Charles Kenneth Harris
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Patent number: 6207946Abstract: A variable intensity lighting system for use with a machine vision apparatus for capturing high contrast images of articles to be inspected, such as semiconductor packages, includes an LED or optical fiber element and flash lamp array configured in multiple segments which are operable to be controlled as to light output intensity by a programmable intensity control circuit operably connected to a microprocessor. The intensity control circuit includes multiple digital potentiometers operable to control selected segments of the lighting array. The control circuit is adapted to control up to 64 segments of the lighting array individually at 64 incremental intensity levels, respectively. The control circuit may include a light failure module to detect a segment failure or a reversed connection.Type: GrantFiled: July 26, 1999Date of Patent: March 27, 2001Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Noor Ashedah Binti Jusoh, Tan Seow Hoon, Sreenivas Rao
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Patent number: 6178861Abstract: Apparatus for cutting single or multiple semiconductor packages from a multilayer substrate wherein the semiconductor packages are partially encapsulated by an elastomer sealant layer disposed on a polymer film layer of the substrate. The apparatus includes upper and lower die assemblies mounted for movement relative to each other on a support base. The upper die assembly includes an actuator and a die block supporting plural sets of cutter blades arranged in patterns to cut rectangular shaped semiconductor packages out of the substrate in a single cutting operation at a single station. The lower die assembly includes plural punch members movable relative to a die block, which includes a support surface for supporting the substrate in a predetermined position as determined by spaced apart locator pins on the lower die assembly registerable with corresponding locator holes in a carrier frame for the substrate.Type: GrantFiled: February 1, 2000Date of Patent: January 30, 2001Assignee: Semiconductor Technologies & Instruments, Inc.Inventor: Tan Huek Choy
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Patent number: 6173632Abstract: Apparatus for cutting single or multiple semiconductor packages from a multilayer substrate wherein the semiconductor packages are partially encapsulated by an elastomer sealant layer disposed on a polymer film layer of the substrate. The apparatus includes upper and lower die assemblies mounted for movement relative to each other on a support base. The upper die assembly includes an actuator and a die block supporting plural sets of cutter blades arranged in patterns to cut rectangular shaped semiconductor packages out of the substrate in a single cutting operation at a single station. The lower die assembly includes plural punch members movable relative to a die block, which includes a support surface for supporting the substrate in a predetermined position as determined by spaced apart locator pins on the lower die assembly registerable with corresponding locator holes in a carrier frame for the substrate.Type: GrantFiled: November 23, 1998Date of Patent: January 16, 2001Assignee: Semiconductor Technologies & Instruments, Inc.Inventor: Tan Huek Choy
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Patent number: 6128034Abstract: An inspection system determines if leads of a semiconductor device are in proper positions. Images from at least two sides of the semiconductor device are captured along with calibration marks formed in the side of a track upon which the semiconductor device is mounted. All leads and calibration marks are captured in a single video image, the images from one side of the semiconductor device being off set from the image from the other side.Type: GrantFiled: February 18, 1994Date of Patent: October 3, 2000Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Charles K. Harris, Michael C. Zemek
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Patent number: 6118540Abstract: A computer vision apparatus and methods for automatically inspecting 2-dimensional (2D) and 3-dimensional (3D) criteria of objects using a single camera and laser sources. A camera views the object under inspection which is illuminated by a first source of light to highlight the region of interest. This provides image data for 2d analysis by a computer coupled to the system. Subsequently, multiple laser sources mounted on a positioner provide the illumination for collecting images for 3 dimensional analysis. A computer with a monitor is connected to the camera to perform the inspection and analysis and for operator supervision of the system. Specific implementations provided refer to embodiments for inspecting packaged semiconductor devices such as Ball-Grid Arrays (BGAs) packages and Quad Flat Packages (QFPs) packages for package mark inspection, package defect inspection, and solder ball or lead defects.Type: GrantFiled: July 11, 1997Date of Patent: September 12, 2000Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Rajiv Roy, Michael C. Zemek, Weerakiat Wahawisan
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Patent number: 5956134Abstract: A system for transporting and inspecting, seriatim, semiconductor devices with plural prong type or solder ball type leads includes a head for transporting the semiconductor devices from one support structure, such as a tray or tube, to a second support structure, such as a tray or tape, and wherein two dimensional and three dimensional measurements of the positional accuracy of the leads is carried out during the transport process. The inspection apparatus is interposed in the transport path and includes a first optical sensor such as a CCD camera oriented to capture a two dimensional image of the semiconductor device package and compare the image with a predetermined two dimensional image store in a central processing unit (CPU).Type: GrantFiled: April 28, 1998Date of Patent: September 21, 1999Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Rajiv Roy, Michael D. Glucksman, Weerakiat Wahawisan, Paul Harris Hasten, Charles Kenneth Harris, George Charles Epp
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Patent number: 5838434Abstract: The invention is to a calibration unit (11) for use with a moveable scale reference (9) for calibration of semiconductor package outlines, the calibration unit (11) is a monolithic rectangular block which has a plurality of legs (12) formed on and integal with said rectangular block and having spacing independent from the leads on a semiconductor device.Type: GrantFiled: December 26, 1996Date of Patent: November 17, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: David A. Skramsted, Clyde M. Guest, III, Dennis M. Botkins
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Patent number: 5826630Abstract: An electronic device package lead conditioning method and system corrects bowed-in J-leads (36) of an electronic device package (30) by inserting between a bowed-in J-lead (36) and electronic device package (36) a comb-like tooth (42) having a graduating-width edge, the graduating width edge graduating from a minimum width (112) to a maximum width (114). The minimum width permits the graduating width edge (112) to be inserted into a space (110) separating the bowed-in J-lead (36) from electronic device package (30). The maximum width (114) at least equals the width of a desired spacing for the bowed-in J-lead (36) from the electronic device package (30) for correcting for the bowed-in-condition of the bowed-in J-lead (36).Type: GrantFiled: September 24, 1997Date of Patent: October 27, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Troy D. Moore, Dennis M. Botkin
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Patent number: 5777886Abstract: A lead conditioning system (10) conditions leads (74) of electronic component package (30) and includes a rotary table (16) for holding electronic component package (30) and making accessible the leads (74). A conditioning tool (20) includes conditioner arm (34) and conditioner blade (70) that selectively contacts a predetermined number of the leads (74). A manipulator (22) moves conditioning tool (20) to positions that contact a predetermined number of leads (74) to condition leads (74). A control system (24) controls the operation of manipulator (22).Type: GrantFiled: July 14, 1994Date of Patent: July 7, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Michael D. Glucksman, Weerakiat Wahawisan, Troy D. Moore, Paul H. Hasten, Dennis M. Botkin, James E. Loveless, Joseph Antao, Michael C. Zemek, Rajiv Roy
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Patent number: 5745593Abstract: Burr inspection system (120) inspects an electrical lead for a burr (112) in association with the operation of a machine vision lead inspection system (10) and includes machine vision circuitry (50) for forming an image (70) of the electrical lead (72) using machine vision lead inspection system (10). Edge detecting instructions (120) associate with machine vision circuitry (50) for determining a plurality of edges (89, 91) associated with the electrical lead (72). Scan line determining instructions (128) calculate a plurality of scan lines (88, 90) each corresponding to the contour of a selected one of the plurality of edges (89, 91). The scan lines (88, 90) are separated from edges (88, 90) and image (70) by a preselected distance (92). Inspecting circuitry (130) inspects each scan line (88, 90) to detect whether a burr image (112) crosses the scan line (88, 90) to determine the presence of a burr on the electrical lead.Type: GrantFiled: July 25, 1996Date of Patent: April 28, 1998Assignee: Semiconductor Technologies & Instruments, Inc.Inventors: Weerakiat Wahawisan, Rajiv Roy