Patents Assigned to Semiconductor Technology Academic Research Center
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Publication number: 20160226656Abstract: According to one embodiment, a phase detector includes an amplifier and an analog-to-digital converter. The amplifier amplifies a voltage of a signal which is output from a digitally-controlled oscillator and is held based on a reference signal. The analog-to-digital converter converts the voltage amplified by the amplifier into a digital signal, based on the reference signal.Type: ApplicationFiled: August 20, 2015Publication date: August 4, 2016Applicant: Semiconductor Technology Academic Research CenterInventor: Kenichi OKADA
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Patent number: 8963124Abstract: At least first and second Si1-xGex (0?x?1) layers are formed on an insulating film. At least first and second material layers are formed correspondingly to the at least first and second Si1-xGex (0?x?1) layers. A lattice constant of the first Si1-xGex (0?x?1) layer is matched with a lattice constant of the first material layer. A lattice constant of the second Si1-xGex (0?x?1) layer is matched with a lattice constant of the second material layer.Type: GrantFiled: March 17, 2009Date of Patent: February 24, 2015Assignee: Semiconductor Technology Academic Research CenterInventors: Masanobu Miyao, Hiroshi Nakashima, Taizoh Sadoh, Ichiro Mizushima, Masaki Yoshimaru
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Patent number: 8941524Abstract: A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.Type: GrantFiled: May 1, 2013Date of Patent: January 27, 2015Assignee: Semiconductor Technology Academic Research CenterInventors: Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshihiro Konishi, Shintaro Izumi, Keisuke Okuno
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Patent number: 8896378Abstract: A differential amplifier circuit includes a differential operational amplifier that includes a differential pair circuit and operates based on a constant bias current supplied from a bias current source circuit, and the differential amplifier circuit includes a bias current generator circuit. A current monitor circuit detects two currents flowing through the differential pair circuit in correspondence with differential input voltages inputted to the differential pair circuit, and detects a minimum current of the two currents for a difference voltage of the differential input voltages as a monitored current. A current comparator circuit compares the monitored current with the constant bias current.Type: GrantFiled: January 29, 2013Date of Patent: November 25, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuya Hirose, Yuji Osaki, Yumiko Tsuruya, Osamu Kobayashi
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Patent number: 8860511Abstract: A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.Type: GrantFiled: November 8, 2012Date of Patent: October 14, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Kenichi Okada, Ahmed Magdi Hassan Musa
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Patent number: 8829985Abstract: According to one embodiment, a time difference amplifier circuit includes the first amplifier including first positive and negative inputs and first positive and negative outputs, the second amplifier including second positive and negative inputs and second positive and negative outputs, first to fourth wirings, a selection circuit including the first selection element connecting the first or fourth wirings to the second positive input, and the second selection element connecting the second or third wirings to the second negative input, and a control circuit connecting the amplifiers by the first and second wirings or by the third and fourth wirings.Type: GrantFiled: August 31, 2012Date of Patent: September 9, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Kiichi Niitsu, Naohiro Harigai, Masato Sakurai, Haruo Kobayashi
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Patent number: 8803725Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.Type: GrantFiled: April 15, 2013Date of Patent: August 12, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Yuji Osaki, Tetsuya Hirose
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Publication number: 20140219355Abstract: A motion estimation device that reduces computational complexity while maintaining high prediction performance includes: block search means searching for a reference block that most approximates a prediction target block within a search range in a past direction frame F (?) or in a future direction frame F (+); search center setting means setting a search center in F (?) and F (+); and search range setting means setting a search range around the search center in F (?) and F (+), wherein the search range setting means sets a relatively large or small search range when F (0) is a P frame and switches assignment of large and small search ranges sequentially between two neighboring prediction target blocks, and the search center setting means sets a position identified by a motion vector predictor as a search center for a frame to which the relatively small search range is assigned.Type: ApplicationFiled: September 30, 2013Publication date: August 7, 2014Applicant: Semiconductor Technology Academic Research CenterInventors: Satoshi GOTO, Jinjia Zhou, Dajiang Zhou
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Patent number: 8779951Abstract: According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.Type: GrantFiled: February 14, 2013Date of Patent: July 15, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi
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Patent number: 8780010Abstract: A metamaterial including at least one spiral conductor. Only a magnetic permeability selected from among an effective dielectric constant and the magnetic permeability of the metamaterial becomes negative, so that the metamaterial have a negative refractive index characteristic. The material includes a plurality of unit cells arrayed in one of one-dimensional direction, two-dimensional directions, and three-dimensional directions. Each of the unit cells includes a dielectric substrate having first and second surfaces disposed in a substantially parallel relationship, and first and second spiral conductors. The first spiral conductor is formed on the first surface of the dielectric substrate, and the second spiral conductor is formed in one of a same direction as and an opposite direction to the first spiral conductor, on the second surface of the dielectric substrate, to oppose the first spiral conductor and to be electromagnetically coupled with the first spiral conductor.Type: GrantFiled: August 30, 2011Date of Patent: July 15, 2014Assignee: Semiconductor Technology Academic Research CenterInventor: Atsushi Sanada
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Patent number: 8709939Abstract: A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.Type: GrantFiled: October 2, 2012Date of Patent: April 29, 2014Assignees: Semiconductor Technology Academic Research Center, National University Corporation Tohoku UniversityInventors: Junichi Koike, Yoshito Fujii, Jun Iijima, Noriyoshi Shimizu, Kazuyoshi Maekawa, Koji Arita, Ryotaro Yagi, Masaki Yoshimaru
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Patent number: 8692623Abstract: A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.Type: GrantFiled: August 22, 2012Date of Patent: April 8, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Seichiro Shiga, Tetsuya Hirose, Yuji Osaki
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Patent number: 8692701Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.Type: GrantFiled: August 30, 2012Date of Patent: April 8, 2014Assignee: Semiconductor Technology Academic Research CenterInventors: Shoji Kawahito, Sung Wook Jung, Osamu Kobayashi, Yasuhide Shimizu, Takahiro Miki, Takashi Morie, Hirotomo Ishii
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Publication number: 20140021987Abstract: Provided is an injection-locked-type frequency-locked oscillator capable of stable operation and exhibiting low phase noise. This injection-locked-type frequency-locked oscillator comprises: a locked loop (10) provided with a first injection-locked-type signal-controlled oscillator (14); and a second injection-locked-type signal-controlled oscillator (20). In the first injection-locked-type signal-controlled oscillator (14), an output frequency signal is made variable by an oscillation frequency control signal, and no reference clock signal is injected.Type: ApplicationFiled: March 12, 2012Publication date: January 23, 2014Applicant: Semiconductor Technology Academic Research CenterInventor: Kenichi Okada
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Patent number: 8618870Abstract: The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.Type: GrantFiled: June 11, 2010Date of Patent: December 31, 2013Assignee: Semiconductor Technology Academic Research CenterInventors: Toshiro Hiramoto, Takayasu Sakurai, Makoto Suzuki
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Patent number: 8614570Abstract: A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.Type: GrantFiled: July 28, 2011Date of Patent: December 24, 2013Assignee: Semiconductor Technology Academic Research CenterInventors: Tetsuya Hirose, Yuji Osaki
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Patent number: 8600443Abstract: A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.Type: GrantFiled: July 12, 2012Date of Patent: December 3, 2013Assignee: Semiconductor Technology Academic Research CenterInventors: Hiroshi Kawaguchi, Masahiko Yoshimoto, Shintaro Izumi
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Publication number: 20130307713Abstract: A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.Type: ApplicationFiled: May 1, 2013Publication date: November 21, 2013Applicant: Semiconductor Technology Academic Research CenterInventor: Semiconductor Technology Academic Research Center
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Patent number: 8587336Abstract: A reconfigurable logic block has a first circuit that configures an arithmetic circuit and a second circuit that configures a circuit outside of the arithmetic circuit. A plurality of different circuits are configured by changing the settings of predetermined signals in the first and second circuits.Type: GrantFiled: November 14, 2006Date of Patent: November 19, 2013Assignee: Semiconductor Technology Academic Research CenterInventors: Toshinori Sueyoshi, Masahiro Iida, Motoki Amagasaki, Kazuhiko Taketa, Taketo Heishi, Nobuharu Suzuki
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Publication number: 20130271308Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.Type: ApplicationFiled: April 15, 2013Publication date: October 17, 2013Applicant: Semiconductor Technology Academic Research CenterInventor: Semiconductor Technology Academic Research Center