Abstract: A semiconductor chip testing apparatus is disclosed. The semiconductor chip testing apparatus includes: an upper socket unit which is formed therein with a receiving space receiving an upper semiconductor chip, holds a lower semiconductor chip using a suction airflow passing around the upper semiconductor chip in the receiving space, and electrically connects the lower semiconductor chip to the upper semiconductor chip; a blade block coupled to the upper socket unit to deliver a vacuum pressure for generating the suction airflow in the receiving space; and a lower socket unit on which the lower semiconductor chip held by the upper socket unit is seated, and which is electrically connected to the seated lower semiconductor chip.