Abstract: An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAM's), which may be written into, or read from in conventional fashion. In a recognition mode, information is read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are then communicated back to the processor.In accordance with specific aspects of the present invention, masking and/or multiwrite features are provided to permit bit reading/writing/searching, rapid memory writing, to facilitate logical and arithmetic data processing and the like.