Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.

Abstract: A Junction Barrier Schottky (JBS) diode includes an N-type epitaxial layer disposed on SiC substrate, P+ wavy regions are disposed in the epitaxial layer adjoining a top planar surface, each of which is separated from an adjacent one of the wavy regions by a Schottky barrier contact region. P+ island regions are disposed in the Schottky barrier contact regions. A top metal layer is disposed along the top planar surface in direct contact with the Schottky barrier contact regions, the P+ wavy regions, and the P+ island regions, the top metal layer comprising the anode of the JBS diode. A bottom metal layer is disposed beneath the SiC substrate. The bottom metal layer comprises the cathode of the JBS diode.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.

Abstract: A Schottky diode includes an upper region having a first doping concentration of a first conductivity type, the upper region disposed above the SiC substrate and extending up to a top planar surface. First and second layers of a second conductivity type are disposed in the upper region adjoining the top planar surface and extending downward to a depth. Each of the first and second layers has a second doping concentration, the depth, first doping concentration, and second doping concentration being selected such that the first and second layers are depleted of carriers at a zero bias condition of the Schottky diode. A top metal layer disposed along the top planar surface in direct contact with the upper region and the first and second layers is the anode, and bottom metal layer disposed beneath the SiC substrate is the cathode, of the Schottky diode.

Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.

Abstract: A silicon carbide MOSFET includes a plurality of first and second trenches each of which extends a predetermined vertical distance from the top of a source down through a body region and into a current spreading layer (CSL). An insulated gate member is disposed in each first trench. The first trenches are each arranged in a wave-shaped pattern that extends in first and second lateral directions. Each of the second trenches is disposed between a pair of adjacent first trenches in the first lateral direction. A shielding region extends vertically from the bottom of each of the second trenches down into a drift region. A top metal layer fill each of the second trenches and electrically contacts the source region, the body region, the CSL, and the shielding region. A bottom metal layer electrically contacts the drain region.

Abstract: A silicon carbide MOSFET includes first and second source regions respectively disposed in the first and second well regions. Each of the first and second source regions extends up to a top surface of the substrate. First and second channel regions of the respective first and second well regions laterally separate the first and second source regions from a JFET region by a channel length. The first and second channel regions extend up to the top surface. The first and second channel regions are each arranged in a wave-shaped pattern at the top surface of the substrate. The wave-shaped pattern extends in first and second lateral directions. In an on-state, current flows laterally from the first and second source regions to the JFET region, and then in a vertical direction down through an extended drain region to the drain region.