Abstract: An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate includes a first PMOS switch controlled by a voltage of a second control node, second PMOS switch controlled by a control voltage, a first control switch unit controlling voltages of first and second control nodes, a first NMOS switch controlled by a voltage of a fourth control node, a second NMOS switch controlled by the control voltage und, and a second control switch unit controlling voltages of third and fourth control nodes.

Abstract: Proposed is an analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate according to an embodiment of the present disclosure, the analog switch circuit including: a first PMOS switch controlled by a voltage of a second control node; a second PMOS switch controlled by a control voltage; a first control switch unit configured to control voltages of first and second control nodes; a first NMOS switch controlled by a voltage of a fourth control node; a second NMOS switch controlled by the control voltage und; and a second control switch unit configured to control voltages of third and fourth control nodes. According to the embodiment of the present disclosure, the successive approximation register analog-to-digital converter may minimize leakage current and realize a wide sampling rate by controlling a voltage of each terminal of an analog switch connected to each of capacitors.

Abstract: The present invention relates to a sensor-integrated chip for a CCD camera in which a CCD sensor, an H/V driver for driving the CCD sensor, and an ISP (Image Signal Process) chip, which inputs a control signal for driving the CCD sensor to the H/V driver and allows a video to be displayed on a monitor (not shown) in response to an output signal from the CCD sensor, are stacked and connected with each other by inter-pad wire bonding into one IC package to be one chip, by an SIP (system In Package) method.

Abstract: The present invention relates to a sensor-integrated chip for a CCD camera in which a CCD sensor, an H/V driver for driving the CCD sensor, and an ISP (Image Signal Process) chip, which inputs a control signal for driving the CCD sensor to the H/V driver and allows a video to be displayed on a monitor (not shown) in response to an output signal from the CCD sensor, are stacked and connected with each other by inter-pad wire bonding into one IC package to be one chip, by an SIP (system In Package) method.