Abstract: A matrix assembly includes: —a matrix of resistive components (5), the resistance values of which represent the coefficients of a discrete Fourier matrix, wherein values representing a first set of input values (1) can be applied to word lines (2) of the matrix, and values representing a second set of output values (3) can be applied to the bit lines (4) of the matrix, the input values (1) being defined by means of phase or amplitude; and —a current amplifier which sums the output values (3) and can be connected to the bit lines (4). The aim of the invention is to allow for an implementation which reduces the number of matrices for a discrete Fourier transform. This aim is achieved in that the matrix assembly also contains capacitive elements, more particularly memcapacitive elements, which can store a capacitive value.

Abstract: A capacitive synaptic component consisting of a layered structure composed of a gate electrode, having a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. A method for writing and reading the component is also disclosed. The component addresses a high capacitive deviation ratio without changing the plate spacing, the surface area or the relative permittivity or limiting the lateral scalability by the intermediate layer having adjustable shielding behaviour in an electric field, proceeding from the gate electrode towards the readout electrode, and the intermediate layer having one or more suitable contacts that produce a charge flow into or a charge flow out of the intermediate layer.

Abstract: A method and arrangement for performing a vector-matrix multiplication by synaptic components includes—a matrix arrangement of components in a differential arrangement, which are periodically charged and discharged; and—a clock generator, which connects the bit lines alternately to a charge integration amplifier or to a ground by means of a changeover switch. The method and arrangement addresses the problem of implementing a switched capacitor arrangement which uses capacitive, resistive or capacitive-resistive components and which uses different variations of an alternating voltage signal as an input variable. The word lines of the matrix are connected to one or more oscillators and the clock generator either reacts to rising or falling voltages of the oscillators or reacts to a positive or negative value range of the voltage of the oscillators.

Abstract: A capacitive synaptic component consisting of a layered structure composed of a gate electrode, having a first dielectric layer connected to the gate electrode, a second dielectric layer and a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. A method for writing and reading the component is also disclosed. The component addresses a high capacitive deviation ratio without changing the plate spacing, the surface area or the relative permittivity or limiting the lateral scalability by the intermediate layer having adjustable shielding behaviour in an electric field, proceeding from the gate electrode towards the readout electrode, and the intermediate layer having one or more suitable contacts that produce a charge flow into or a charge flow out of the intermediate layer.