Abstract: A circuit is disclosed having a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal.

Abstract: A circuit is disclosed having a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal.

Abstract: A circuit is disclosed having a component having repeatable distortion characteristics; and a drive circuit for providing a drive signal and comprising a non-linear filter for pre-compensating for distortion introduced by the component having repeatable distortion characteristics in response to the drive signal, the distortion having a non-linear response to the drive signal.

Abstract: A transmitter transmits a raster-type video signal. For each one of a plurality of active video segments of a frame of the video signal, the transmitter derives redundant data from the respective active video segment and inserts the redundant data into a horizontal blanking segment of the video signal.

Abstract: Systems and methods are provided for generating a pseudo-random bit sequence at an output frequency using a clock signal operating at a first frequency that is lower than the output frequency. A first bit sequence of a particular type is generated using a clock signal operating at a first frequency. A second bit sequence is generated using the clock signal operating at the first frequency, where the second bit sequence is a delayed version of the first bit sequence. A delayed version of the first bit sequence is generated using the second bit sequence and another bit sequence, wherein the delayed version is delayed based on the particular type and a difference between the output frequency and the first frequency. The first bit sequence and the delayed version are combined to generate a pseudo-random bit sequence at the output frequency.

Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

Abstract: A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal.

Abstract: A video processing system may include: a video deserializer having (i) an input for receiving a serial data stream containing video data and (ii) a serial to pseudo-parallel converter, coupled to the serial data stream, for generating from the serial data stream a plurality of serial data output streams through a plurality of serial output lanes; a video serializer having (i) a plurality of inputs for receiving serial data streams and (ii) a pseudo-parallel to serial converter, coupled to the plurality of input serial data streams, for generating a single serial data stream from the plurality of input serial data streams; and a programmable video processing device, coupled to the video deserializer and the video serializer, and having a plurality of interface pins for receiving the plurality of serial output lanes from the deserializer and for transmitting the plurality of serial data streams to the serializer.

Abstract: A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

Abstract: A folding adaptive equalizer is provided. The equalizer comprises an equalizer core and an automatic gain control loop. The equalizing transfer function of the equalizer core is modulated by one or more gain control signals generated by the automatic gain control loop and by a folding signal generated by the automatic gain control loop. When the folding signal is inactive, an increase in the gain control signals produces an increase in the high-frequency, high-bandwidth gain of the transfer function of the equalizer core. When the folding signal is active, further gain can be applied by decreasing the gain control signals, which produces a frequency-shift in the transfer function of the equalizer core toward lower bandwidth and an increase in the high-frequency, low-bandwidth gain of the transfer function of the equalizer core.

Abstract: A crosspoint selector switch for simultaneously supporting multiple data formats having different switch reconfiguration timing requirements, comprising; a configurable switch section for selectively connecting outputs thereof to receive data from respective inputs thereof in response to operational switch data; and a configuration section operatively connected to provide the operational switch data to the switch section, the configuration section storing switch configuration data supporting multiple different configurations of the switch section, the configuration section being operative to receive different operational update commands each associated with a different configuration for the switch section and update the operational switch data from the stored switch configuration data to reconfigure the switch section in dependence on which of the different operational update commands is received.

Abstract: An adapter is provided for coupling between a Thunderbolt® compliant connector and a pluggable optical transceiver connector of a pluggable optical transceiver host board, the pluggable optical transceiver connector for connecting with an optical pluggable transceiver and other than a connector compliant with a Thunderbolt® standard. The adapter has a first connector for mating with the pluggable optical transceiver connector and a second connector for coupling with a Thunderbolt compliant connector.

Abstract: Systems and methods are provided herein for interfacing a first multi-media digital device with a second multi-media digital device. An exemplary method includes the steps of: (i) converting a plurality of differential digital content channels from the first multi-media digital device into a plurality of single-ended digital content channels; (ii) transmitting the plurality of single-ended digital content channels from the first multi-media digital device to the second multi-media digital device via one or more coaxial cables; and (iii) receiving the single-ended digital content channels from the one or more coaxial cables and converting the single-ended digital content channels back into a plurality of differential digital content channels that are supplied to the second multi-media digital device.