Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist.

Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist; wherein elaborating comprises word-oriented elaborating.

Abstract: An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree; (b) elaborating the parse tree to create a word-oriented netlist; and (c) inferring complex components from the word-oriented netlist.

Abstract: A method measures a resistance in a test structure to determine the sheet resistivity of a test structure. In one embodiment, a family of test structures is provided to determine the effective sheet resistivity of a conductor as a function of its width. The method is applicable to conductors in manufacturing processes in which “slots” or “islands” are created in the conductor to prevent dishing during chemical-mechanical polishing.

Abstract: A novel parasitic extraction system includes an interconnect primitive library that has a parameterized inductance function for at least one conducting layer of the integrated circuit. A parasitic extractor analyzes structures within a selected distance of a selected conductor within the integrated circuit and determines parasitic inductance values for the selected conductor using the parameterized inductance function of the interconnect primitive library. Using this parasitic extraction system, parasitic impedances, including inductance, may be extracted for an integrated circuit layout, thus allowing more accurate modeling and timing analysis of the integrated circuit layout to be obtained.

Abstract: A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.

Abstract: A method models conductive regions of a semiconductor substrate in conjunction with conductors in the interconnect structures above the semiconductor substrate. Such a method allows highly accurate extraction of capacitance in planar (e.g., shallow trench isolation) and non-planar (e.g., thermal oxide isolation) semiconductor structures. This method is particularly applicable to modeling dummy diffusion regions prevalent in shallow trench isolation structures. An area-perimeter approach simplifies calculation of capacitance without using a 3-dimensional electric field solver. A method is also provided for extracting a capacitance associate with a contact, or a connecting conductor between two conductor layers.

Abstract: A method provides estimations of physical interconnect process parameter values in a process for manufacturing integrated circuits. The method includes fabricating test structures each providing a value of a measurable quantity corresponding to a value within a range of values of the physical interconnect process parameters. In some embodiments, the measured value is used to derive the values of the physical interconnect process parameters, either by a numerical method using a field solver, or by a closed-form solution. The values of physical interconnect process parameters involving physical dimensions are also obtained by measuring photomicrographs obtained using a scanning electron microscope from cross sections of test structures. In some embodiments, a family of test structures corresponding to a range of conductor widths and a range of spacings between conductors are measured.