Abstract: Physical memory is accessed by associating identified memory with a window of virtual address space whose size and location are specified by an application program. In the typical application of the invention, the virtual window is smaller in size than the associated memory. One or more virtually-windowed address translations are then established between portions of the windowed address space and the corresponding portions of the physical memory. Additional physical memory can be accessed with the same virtual address space by establishing new virtually-windowed address translations with other portions of the physical memory. In the preferred embodiment of the invention, the physical memory is identified, attached to the virtual window, and the address translation is established by the computer's operating system in response to a series of system calls from an application program.

Abstract: For a multiprocessor computer having shared memory distributed across multiple nodes, a method and system for dynamically replicating data such as program text stored in memory on a first node to memory on a second node for use by a process executing on the second node. In response to a page fault generated by the process in accessing data, a determination is made whether the data is present in the memory of another node. If so, memory is allocated on the process's node for the data, and the needed data is copied from the other node to the process's node. The process's page table entry for the missing data is then modified to contain the physical address of the allocated memory, where the data is now stored. The method is implemented in a preferred embodiment by using novel data structures linked to the data structures that are typically created when a file is mapped to a process's virtual address space.

Abstract: A multiprocessor system that assures forward progress of local processor requests for data by preventing other nodes from accessing the data until the processor request is satisfied. In one aspect of the invention, the local processor requests data through a remote cache interconnect. The remote cache interconnect tells the local processor to retry its request for data at a later time, so that the remote cache interconnect has sufficient time to obtain the data from the system interconnect. When the remote cache interconnect receives the data from the system interconnect, a hold flag is set. Any requests from other nodes for the data are rejected while the hold flag is set. When the local processor issues a retry request, the data is delivered to the processor and the hold flag is cleared. Other nodes may then obtain control of the data.

Abstract: A method is disclosed for forming resistors that are low cost, easy to manufacture and substantially within 5 percent of their desired value. In one aspect of the method, an electrically resistive material, such as nickel, is deposited directly on an insulating layer, such as a substrate. A conductive material, such as copper, is then deposited on the resistive material. Using photo-imaging, signal traces are formed in the conductive and resistive materials. A resistor is created by forming a gap in the conductive material at a location where the resistor is desired. Current is thereby forced to flow through the resistive material at the location of the gap.

Abstract: An apparatus and method for initializing a shared-memory, multinode multiprocessor computer system. The nodes in the multiprocessor computer system separately and independently run standard PC-based BIOS routines in parallel for initialization of the nodes. These BIOS routines set addresses of hardware components on each node as though the nodes are in a single-node environment. After completion of BIOS, the addresses of the hardware components are reprogrammed to conform with the multinode environment. A master processor then takes control to boot the operating system on the multinode environment.

Abstract: In a digital computer with a cache comprised of N sets labeled 0 to N-1, cache tag memory for each set is divided into primary and mirror parts, each part with sufficient capacity to store a number of cache tags equal to the number of cache blocks storable in a cache memory associated with each set. Every modification or installation of cache tags in the primary part of a set x is accompanied or followed by identical modification or installation of cache tags in the mirror part of a set F(x), where F is a one-to-one function that maps the set of integers from 0 to N-1 onto itself. Cache tag lookup retrieves a first set of N cache tags from the primary part of each cache tag memory, and parity checking is performed on each tag. If a parity error is found, a set of cache tags is retrieved from the mirror part of the cache tag memories, and parity checking is again performed. If no error is found, cache processing proceeds normally.

Abstract: A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request.

Abstract: A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position.

Abstract: A self-retaining rack slide for rack-mounted computer systems. The rack slide includes a slide and a rack mounting member which are fastened together while permitting relative longitudinal movement between the two parts. A biasing mechanism such as a spring is fastened to the mounting member and the slide to urge the two lengthwise apart to increase the length of the slide rack. A complementary slide fastened to a rack component slidingly engages the rack slide to permit the component to be slid into and out of the rack.

Abstract: Local memory on a node in a multinode, multiprocessor computer system with distributed shared memory and a remote cache is efficiently updated through the use of a combined tag stored in a tag cache. In response to a local processor request for access to local memory that does not contain a current copy of the data requested, a combined tag is formed from a memory tag and a remote cache tag. The combined tag allows the node to operate in accordance with the network protocol such as the Scalable Coherent Interface (SCI) while the memory is being updated, acting as memory in response to requests from other nodes to the memory and as a cache in response to requests from other nodes to the remote cache. In this way the memory is updated quickly and the remote cache is not required to store data that is better stored in the local memory.

Abstract: A substantially zero overhead mutual-exclusion apparatus and method (90, 120) is provided that allows concurrent reading and updating data while maintaining data coherency. That is, a data reading process executes the same sequence of instructions that would be executed if the data were never updated. Rather than depending exclusively on overhead-imposing locks, this mutual-exclusion mechanism tracks an execution history (138) of a thread (16, 112) to determine safe times for processing a current generation (108, 130, 131) of data updates while a next generation (110, 132, 133) of data updates is concurrently being saved. A thread is any locus of control, such as a processor. A summary of thread activity (106, 122) tracks which threads have passed through a quiescent state after the current generation of updates was started.

Abstract: A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position.

Abstract: A compiler and method for optimizing a program based on branch probabilities, branch frequencies and function frequencies. A number of algorithms executed by the compiler determine statically from the program code the probabilities that branches with the program are taken and how often the branches are taken. With this information, the compiler arranges the object code in memory to improve execution of the program. The frequency of functions within the code may be determined from the branch probability and branch frequency information. The compiler uses the function frequency information to arrange the functions in a desirable order, such as storing function pairs with the highest global call frequencies on the same memory page. This minimizes the number of calls to functions that are stored on disk and thus improves the speed of execution of the program.

Abstract: A substantially zero overhead mutual-exclusion apparatus and method (90, 120) is provided that allows concurrent reading and updating data while maintaining data coherency. That is, a data reading process executes the same sequence of instructions that would be executed if the data were never updated. Rather than depending exclusively on overhead-imposing locks, this mutual-exclusion mechanism tracks an execution history (138) of a thread (16, 112) to determine safe times for processing a current generation (108, 130, 131) of data updates while a next generation (110, 132, 133) of data updates is concurrently being saved. A thread is any locus of control, such as a processor. A summary of thread activity (106, 122) tracks which threads have passed through a quiescent state after the current generation of updates was started.

Abstract: A substantially zero overhead mutual-exclusion apparatus and method (90, 120) is provided that allows concurrent reading and updating data while maintaining data coherency. That is, a data reading process executes the same sequence of instructions that would be executed if the data were never updated. Rather than depending exclusively on overhead-imposing locks, this mutual-exclusion mechanism tracks an execution history (138) of a thread (16, 112) to determine safe times for processing a current generation (108, 130, 131) of data updates while a next generation (110, 132, 133) of data updates is concurrently being saved. A thread is any locus of control, such as a processor. A summary of thread activity (106, 122) tracks which threads have passed through a quiescent state after the current generation of updates was started.

Abstract: An apparatus and a method facilitate the sharing of a SCSI address ID between a SCSI initiator and a target device. The SCSI standard does not prohibit ID sharing under a set of operating conditions defined by this invention. The shared ID is preferably used for controlling an environmental monitor device that controls the power of disk drives on the SCSI bus, detects their status and configuration, and monitors environmental conditions within a mass storage system cabinet. Power to individual disk drives is switched under control of the computer operating system so that start-up surge current to the disk drives is limited. This allows defective drives to be powered down and replaced without powering down the remaining good drives. SCSI termination power distribution is improved so that connector reversals can be detected and resulting current surges limited. Termination power control and status is under program control.

Abstract: A computing system (50) includes N number of symmetrical computing engines having N number of cache memories joined by a system bus (12). The computing system includes a global run queue (54), an FPA global run queue, and N number of affinity run queues (58). Each engine is associated with one affinity run queue, which includes multiple slots. When a process first becomes runnable, it is typically attached one of the global run queues. A scheduler allocates engines to processes and schedules the processes to run on the basis of priority and engine availability. An engine typically stops running a process before it is complete. When the process becomes runnable again the scheduler estimates the remaining cache context for the process in the cache of the engine. The scheduler uses the estimated amount of cache context in deciding in which run queue a process is to be enqueued.

Abstract: A computing system (50) includes N number of symmetrical computing engines having N number of cache memories joined by a system bus (12). The computing system includes a global run queue (54), an FPA global run queue, and N number of affinity run queues (58). Each engine is associated with one affinity run queue, which includes multiple slots. When a process first becomes runnable, it is typically attached one of the global run queues. A scheduler allocates engines to processes and schedules the processes to run on the basis of priority and engine availability. An engine typically stops running a process before it is complete. When the process becomes runnable again the scheduler estimates the remaining cache context for the process in the cache of the engine. The scheduler uses the estimated amount of cache context in deciding in which run queue a process is to be enqueued.