Patents Assigned to Sequoia Design Systems
  • Integrated scheme for semiconductor device verification
    Patent number: 6681376
    Abstract: A method for determining device yield of a semiconductor device design, comprises determining statistics of at least one device parameter from at least two device layer patterns; and calculating device yield from the statistics. At least one of the device layer patterns is neither a diffusion layer pattern nor a gate poly layer pattern.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: January 20, 2004
    Assignees: Cypress Semiconductor Corporation, Numerical Technologies, Inc., Sequoia Design Systems
    Inventors: Artur Balasinski, Linard Karklin, Valery Axelrad
  • Integrated scheme for predicting yield of semiconductor (MOS) devices from designed layout
    Patent number: 6562638
    Abstract: A method for determining device yield of a semiconductor device design, includes determining statistics of at least one MOSFET parameter from a gate pattern, and calculating device yield from the at least one MOSFET parameter. The method provides a direct simulation link from device layout to device performance.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: May 13, 2003
    Assignees: Cypress Semiconductor Corp., Cadence Design Systems, Inc., Sequoia Design Systems
    Inventors: Artur Balasinski, Robert C. Pack, Valery Axelrad, Victor Vladimir Boksha