Abstract: A BIST cell having a memory element with an asynchronous input in a logic circuit using a built-in self-test mechanism. The BIST cell includes logic to provide a data signal to the memory element during user mode, a reset value to the memory element during reset mode, a scan signal value to the memory element during scan mode, and the sume of the data, reset and scan values during test mode. The BIST cell also prevents the memory element from being reset during test mode.