Abstract: A BIST clock driver for providing memory elements in a combinational and sequential logic circuit with a global clock signal during user mode and a test clock signal during testing. The clock driver also supplies clock signals to memory circuits that have clock inputs supplied by random logic. The clock driver supplies the random logic with a global clock signal. A clock multiplexor receives the generated clock and the test clock signal and provides the memory element with the generated clock signal during user mode and the test clock during testing of the memory element.

Abstract: A circuit architecture for driving a tri-state bus in a logic circuit that uses a built-in self-test (BIST) mechanism. The architecture includes tri-state drivers which have circuitry to inhibit other drivers from driving the bus when another driver is driving the bus. The architecture includes circuitry to pullup the bus or to allow the bus to retain the last state it was driven to when none of the drivers is driving the bus. This circuitry also drives the bus to a known state during testing of the logic circuit.

Abstract: A process for implementing logic units using base cells and implementing an electrical connection between the logic units in a gate array. The process includes determining a connection path between the base cells and connecting the base cells at the second metalization layer using a portion of the first metalization layer. This is possible due to the gate array having vertical first metalization layer segments of the first metalization layer positioned vertically in the channel between the rows of base cells, wherein each of the vertical segments has vias in the insulation layer between the first metalization layer and the second metalization layer at its endpoints for connecting the metalization layers. Similarly, the individual transistors which comprise the base cell are coupled using the second metalization layer to implement a specific logic unit.

Abstract: A power-on reset circuit for providing a reset signal to an active device on an integrated circuit (IC). The circuit includes a RC circuit for producing a reset signal until its capacitor fully charges. The circuit also includes a voltage detector for preventing the charge from collecting on the capacitor of the RC circuit until the voltage is at a functional level.