Patents Assigned to Sequoia Systems, Inc.
  • Patent number: 5664195
    Abstract: A method is provided for dynamic installation of a driver on a computer system. The computer system has a first operator processor with a first memory and an operating system, a second processor with a second memory and operating code configurable to accept a driver, and a data channel supporting communication between the first processor and the second processor, the first processor sending requests to the second processor for processing.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: September 2, 1997
    Assignee: Sequoia Systems, Inc.
    Inventor: Sanjoy Chatterji
  • Patent number: 5621887
    Abstract: A fault tolerant disk management system supports compound disks which are mirrored, so as to tolerate single point faults in any one physical disk of the compound disk. The system further minimizes the exposure of data stored on such a compound disk arising from additional single point failures in other physical disks of the compound disk. The system may be implemented as a software method for removing a physical disk from a logical compound disk without breaking up the compound disk or any mirror of which the compound disk may be a part. The removed physical disk may then be reinserted into the compound disk and mirror after repair. Further, the system provides fault responses which may be varied in accordance with an indication of criticality of each disk to the system.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: April 15, 1997
    Assignee: Sequoia Systems, Inc.
    Inventor: Sanjoy Chatterji
  • Patent number: 5325062
    Abstract: Apparatus and method are provided for fault detecting in an electrical system such as a redundant or fault-tolerant system. A current receiving device connected in shunt or in series in such a system draws electric current from the electrical system being monitored. During normal operation, while current is still flowing properly through the system being monitored, an appropriate indication such as a continued series of pulses is generated, which is interpreted as indicating proper operation. If that current flow is cut off, indicating a fault condition, then the apparatus and method provide an appropriate signal (such as cutoff of the series of pulses) to a communication system which provides an appropriate indication to an external location. The current receiving device can be a relaxation oscillator together with another device which can be a pulse generator, an L-C energy transfer arrangement, a bridge circuit including an inductor, a two-winding inductor or a capacitor.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: June 28, 1994
    Assignee: Sequoia Systems, Inc.
    Inventors: Gerard E. Bachand, Peter A. Goodwin
  • Patent number: 5115499
    Abstract: Computer system resources shared by several central processing units are allocated by allowing one processing unit to temporarily gain exclusive access to a particular shared resource. Access to a particular resource is controlled by a memory location which contains information representing the current state of the resource and the identity of any processing element currently utilizing the resource. In the case where several resources are interchangeable, the memory location may also contain information regarding the busy/idle states of other interchangeable resources. The memory location can be interrogated by any of the processing elements via command and address information. If the contents of the memory location indicate that the associated resource is not in use, then the interrogating processing element immediately obtains control of the resource.
    Type: Grant
    Filed: January 2, 1991
    Date of Patent: May 19, 1992
    Assignee: Sequoia Systems, Inc.
    Inventors: Jack J. Stiffler, James M. Nolan, Peter Mark, David Harvey
  • Patent number: 4819154
    Abstract: Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity.To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory.
    Type: Grant
    Filed: December 4, 1986
    Date of Patent: April 4, 1989
    Assignee: Sequoia Systems, Inc.
    Inventors: Jack J. Stiffler, Michael J. Budwey, James M. Nolan, Jr.
  • Patent number: 4736376
    Abstract: Encoding/decoding circuitry which processes data and both corrects single errors and detects multiple errors is disclosed. The circuitry is both fail-safe and self-checking in that no internal device failure can alter data without producing improperly encoded outputs and all failures quickly reveal themselves through normal usage even if they do not actually cause any data to be modified. The circuitry can be configured in two identical halves with each half operating on one half of the data so that the circuitry can be advantageously constructed with large scale integrated circuits. Error-detecting information in the form of a syndrome produced by each circuit half is combined with similar syndrome information produced by the other circuit half. The combined syndrome information is then decoded to generate error correction information which is used to modify the data bit outputs to correct detected errors.
    Type: Grant
    Filed: October 25, 1985
    Date of Patent: April 5, 1988
    Assignee: Sequoia Systems, Inc.
    Inventor: Jack J. Stiffler
  • Patent number: 4654819
    Abstract: Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity.To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory.
    Type: Grant
    Filed: June 28, 1985
    Date of Patent: March 31, 1987
    Assignee: Sequoia Systems, Inc.
    Inventors: Jack J. Stiffler, Michael J. Budwey, James M. Nolan
  • Patent number: 4608631
    Abstract: A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas.
    Type: Grant
    Filed: November 19, 1984
    Date of Patent: August 26, 1986
    Assignee: Sequoia Systems, Inc.
    Inventors: Jack J. Stiffler, Richard A. Karp, James M. Nolan, Jr., Michael J. Budwey, David A. Wallace
  • Patent number: 4541094
    Abstract: Circuitry for a fault-tolerant computer is disclosed which circuitry is constructed in two identical halves. Each half, by itself, is not a functionally-complete circuit, however, the two identical halves can be connected together to provide a functionally-complete circuit. Each of the two circuit halves is considerably less complex than a functionally-complete circuit yet, when connected together, the two halves provide fault detection capabilities equivalent to a computer system in which the outputs of two functionally-complete, redundant circuits are compared to detect faults.In particular, each inventive circuit half contains a complete data processing and control unit but only one half of the memory which is necessary for a functionally-complete unit. The processing units on each circuit half operate simultaneously on identical data and the same address information is provided to the memories on each circuit half.
    Type: Grant
    Filed: March 21, 1983
    Date of Patent: September 10, 1985
    Assignee: Sequoia Systems, Inc.
    Inventors: Jack J. Stiffler, Michael J. Budwey, James M. Nolan, Jr.
  • Patent number: 4484273
    Abstract: A multi-processor computer system is disclosed in which processing elements, memory elements and peripheral units can be physically added and removed from the system without disrupting its operation or necessitating any reprogramming of software running on the system. The processing units, memory units and peripheral units are all coupled to a common system bus by specialized interface units. The processing elements are organized into partially independent groups each of which has dedicated interface units, but the processing units share system resources including peripherals and the entire memory space. Within each processing element group at any one time, group supervisory tasks are performed by one of the processors, but the supervisor function is passed among the processors in the group in a sequence to prevent a fault in one processor from disabling the entire group. Communication between groups is accomplished via the common memory areas.
    Type: Grant
    Filed: September 3, 1982
    Date of Patent: November 20, 1984
    Assignee: Sequoia Systems, Inc.
    Inventors: Jack J. Stiffler, Richard A. Karp, James M. Nolan, Jr., Michael J. Budwey, David A. Wallace