Abstract: A programmable element sequence selection circuit which selects a repeatable sequence of elements from a plurality of elements is provided. The sequence selection circuit includes a sequence storage circuit into which a sequence of element identifiers is loaded and accessed.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remain constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily contolled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives coupled to a plurality of small buffers. An Error Correction Controller is coupled to a plurality of X-bar switches, the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

Abstract: A circuit for decoding a high speed Manchester encoded digital communication signal is provided. The circuit includes a pair of latch circuits which are used to detect clock edges in the encoded signal for providing respectively set and reset pulses to a third latch circuit, an output of which comprises the decoded data of the Manchester code signal. Additional logic is provided to extract a clock signal from the Manchester code signal.