Abstract: An inductive current detection circuit for a Direct Current (DC)-DC converter, the DC-DC converter, and a chip are provided. The inductive current detection circuit includes a switching circuit, a first control circuit, a second control circuit, and an output circuit. The switching circuit transfers a voltage at a first end of an inductor of the DC-DC converter to a first node during the period when a first control signal is at an active level. The first control circuit generates a voltage difference equal to a first increment value between a second node and the first node. The second control circuit records a historical voltage positively correlated with a voltage of the first node during the period when a second control signal is at the active level, and generate a voltage difference equal to a second increment value between the second node and the first node according to the historical voltage.

Abstract: A Direct Current (DC)-DC converter, a chip, and an electronic device are provided. The DC-DC converter includes a bootstrap boost circuit, a charge pump boost circuit, a high-side driver circuit, a low-side driver circuit, a high-side power transistor, and a low-side power transistor, wherein the bootstrap boost circuit provides a first boost voltage for the high-side driver circuit; the high-side driver circuit outputs a first high-side driving voltage to a control electrode of the high-side power transistor according to the first boost voltage; the charge pump boost circuit generates a second boost voltage through a charge pump, and outputs a second high-side driving voltage to the control electrode of the high-side power transistor based on the second boost voltage, wherein the second boost voltage is greater than the first boost voltage.

Abstract: A Low Dropout Regulator (LDO) with ripple rejection includes an LDO main circuit, a ripple introduction capacitor, and a first resistor, wherein the LDO main circuit is configured to control an output voltage of the LDO according to a control loop formed by an error amplifier and a power transistor; the ripple introduction capacitor is configured to introduce a ripple at an input end of the LDO into the control loop through the error amplifier; and the first resistor is configured to isolate the ripple at the input end of the LDO from an output end of the LDO. The problems that the structure of a circuit for canceling an LDO output ripple with Feed-Forward Ripple Cancellation (FFRC) is complex, and the stability and transient response of a circuit are affected are solved.

Abstract: The present application discloses a detection circuit and a power management system including the detection circuit. The detection circuits include a threshold voltage generation circuit, a voltage-to-current conversion circuit, and a current-type successive approximation quantizer. The voltage-to-current conversion circuit converts an offset voltage of a signal to be detected into a proportional current with respect to a threshold voltage which is generated by the threshold voltage generation circuit. The current-type successive approximation quantizer obtains a comparison result between the signal to be detected and the threshold voltage, or a quantization result of the signal to be detected within a window by quantizing the proportional current. Thus, the circuit structure is simplified and the cost is reduced.

Abstract: The present application discloses a power management integrated circuit includes an I2C interface circuit and a driving circuit. The I2C interface circuit receives regulation parameters from the host controller. The driving circuit converts a switching signal into a driving signal and applies the driving signal to a control terminal of a power switch in the power management integrated circuit, and that regulates power transmission from the input terminal to an output terminal of the power management integrated circuit by controlling on and off states of the power switch to provide a stable output voltage, the switching signal being obtained according to the regulation parameters. The power management integrated circuit has improved communication accuracy by adjusting a driving speed of the driving circuit and/or a supply voltage of the I2C interface circuit when communication of the I2C interface is interfered.

Abstract: An on-timing circuit includes a current generation module, an inversion delay counteracting module, a capacitor, and a comparator, wherein the current generation module is configured to generate a charging current in direct proportion to a voltage of a switch node after an upper power transistor is turned on; the inversion delay counteracting module is configured to generate a first delay for counteracting an inversion delay of the comparator according to a variable resistance unit and the capacitor, and a resistance value of the variable resistance unit is controlled by an input voltage; the capacitor is configured to be charged by the charging current after the upper power transistor is turned on; and the comparator is configured to compare a ramp voltage corresponding to a ramp voltage node with a first voltage and generate a turn-off signal, and the first voltage is a reference voltage in proportion to an output voltage.

Abstract: A digital-to-analog converter includes a sampling resistor network circuit, an operational amplifier, a feedback resistor, and a compensation current generation circuit. The sampling resistor network circuit controls a sampling resistance value of the sampling resistor network circuit based on a sampling codeword, and generates an output current based on a voltage difference between a first reference voltage and a voltage at a first input terminal of the operational amplifier as well as the sampling resistance value. The compensation current generation circuit generates a compensation current based on the sampling codeword. The compensation current is used to compensate for an offset current generated by an offset voltage in the sampling resistor network circuit in order to make a sum of the compensation current and the offset current equal to a first constant. The first constant is independent of the sampling codeword.

Abstract: A control circuit of a variable-frequency switching converter includes a duty ratio modulation signal generation module, a Constant On Time (COT) trigger signal generation module, and a control module, wherein the duty ratio modulation signal generation module outputs a duty ratio modulation signal to a first end of the control module; the COT trigger signal generation module outputs a COT trigger signal to a second end of the control module when a ripple voltage is less than a ripple reference voltage; and the control module generates a fixed on frequency pulse width signal based on the duty ratio modulation signal and a clock signal when the COT trigger signal is not received, outputs a control signal based on the fixed on frequency pulse width signal, and generates a COT pulse width signal based on the control signal and the COT trigger signal when the COT trigger signal is received.

Abstract: An on-timing circuit includes a current generation module, an inversion delay counteracting module, a capacitor, and a comparator, wherein the current generation module is configured to generate a charging current in direct proportion to a voltage of a switch node after an upper power transistor is turned on; the inversion delay counteracting module is configured to generate a first delay for counteracting an inversion delay of the comparator according to a variable resistance unit and the capacitor, and a resistance value of the variable resistance unit is controlled by an input voltage; the capacitor is configured to be charged by the charging current after the upper power transistor is turned on; and the comparator is configured to compare a ramp voltage corresponding to a ramp voltage node with a first voltage and generate a turn-off signal, and the first voltage is a reference voltage in proportion to an output voltage.

Abstract: An oscillator circuit includes a frequency setting circuit, a first and a second clock signal generating circuit, a clock synchronization circuit, a control circuit, and an output circuit. The first and second clock signal generating circuits generate first and second clock signals respectively. The control circuit outputs a frequency setting signal via a second node, outputs the first clock signal via a sixth node, and outputs the second clock signal via a seventh node when the first frequency selecting signal is at an effective voltage level; otherwise, outputs a second synchronization control signal via the second node, outputs an external synchronization clock signal via the sixth node, and outputs a first clock signal via the seventh node. The clock synchronization circuit generates the first and second synchronization control signals. The output circuit outputs the first or second clock signal.

Abstract: The present disclosure provides a multiphase switching converter and control circuit thereof. The multiphase switching converter includes a plurality of control circuits forming a daisy chain architecture, and to generate a preparatory output signal and a switching control signal for controlling a corresponding switching circuit when receiving a clock signal from a communication bus in the preparatory state, the control circuit is configured to operate in a preparatory state when receiving a preparatory input signal. Only preparatory signals are transmitted between the plurality of control circuits, and a signal for controlling circuit being on is participated by the clock signal generated by a host controller, so that the host controller does not need to track a position of a current unit in real time during a control process of all units, thus greatly simplifying a design of the host controller and reducing a circuit cost.

Abstract: A device module includes first and second conductive layers, and first and second functional layers between the first and second conductive layers. The first functional layer includes a plurality of capacitors and a plurality of via electrodes isolated from the plurality of capacitors. A plurality of inductors are formed in the second functional layer, each arranged along a thickness direction of the second functional layer. Thus, a first terminal of the inductor is electrically coupled with the first conductive layer through corresponding one of the via electrodes, and a second terminal of the inductor is electrically coupled with the second conductive layer. The device module simplifies the layout and wiring of a multi-phase circuit by directly installing the driver on the multi-inductor array with the pins being arranged longitudinally, and improves the effective utilization of inductor and capacitor materials.

Abstract: The present invention discloses an analog-to-digital converter and an operating method thereof. The analog-to-digital converter includes a plurality of sub-periods in one conversion frame, and performs at least the following operations in each sub-period: a residual charge storage phase, an integration phase, a charge redistribution phase, and an SAR conversion phase. The analog-to-digital converter includes a capacitive digital-to-analog converter and an auxiliary capacitor. The auxiliary capacitor stores residual charge generated by the capacitive digital-to-analog converter in a previous sub-period at the residual charge storage phase. A weight capacitor array of the capacitive digital-to-analog converter integrates an input current signal at the integration phase. The integration charge of the current sub-period is transferred to the weight capacitor array at the charge redistribution phase.

Abstract: A Boost-type converter and a driving circuit for driving a high-side switching transistor thereof includes an input voltage sensing unit, an oscillator, a logic unit, and a high-side driving unit. The logic unit receives an input voltage detection signal, a clock signal and a pulse width modulated signal, and generates a control signal according to the input voltage detection signal, the clock signal and the pulse width modulated signal. The high-side driving unit generates a driving signal of a high-side switching transistor for driving the high side switching transistor according to the control signal. When the input voltage is greater than a predetermined voltage, the high-side driving unit controls the high-side switching transistor to be in a weak-conduction state or off state for a time period of an inductor current discharge phase.

Abstract: A power conversion circuit of a multi-phase power supply, a multi-phase power supply and a control method is provided. The power conversion circuit includes a PWM signal generating circuit, a driving circuit and a power circuit. The PWM signal generating circuit receives a counting code, generates a pulse width modulation signal when a count value characterized by the counting code is equal to their identification numbers, and controls on and off states of the switching transistor in the power circuit. Therefore, a plurality of phases of power conversion circuits in the multi-phase power supply may share one timing circuit to control on times of respective ones of the power conversion circuits, which is beneficial for reducing complexity and cost of the controller, and reducing circuit size and cost of the multi-phase power supply, and for implementation of a multi-phase power supply with higher phase numbers.

Abstract: Disclosed is a bandwidth adjustment circuit and a bandwidth adjustment method of an operational amplifier. The circuit comprises: a bias current generation unit connected with a bias current input terminal of the operational amplifier and used for providing a bias current to the operational amplifier; a current adjustment unit, connected with the bias current generation unit and an output terminal of the operational amplifier, respectively, and used for adjusting the bias current according to an output voltage of the operational amplifier to realize bandwidth adjustment on the operational amplifier. The bandwidth adjustment circuit and the bandwidth adjustment method can dynamically adjust the bandwidth of the operational amplifier according to the output voltage, not only improving stability when the output voltage of the operational amplifier is low, but also ensuring excellent performance of the operational amplifier when the output voltage is high.

Abstract: Disclosed is an operational amplifier, including: a loading input transistor pair; a differential input transistor pair, which is connected with the loading input transistor pair, has a non-inverting input terminal receiving a non-inverting input signal, and has an inverting input terminal receiving an inverting input signal; a controller unit, generating a first control signal according to the non-inverting input signal and a second control signal according to the inverting input signal; a regulator unit, connected between the differential input transistor pair and ground, controlled by the first control signal and the second control signal, and select an on/off state of the regulator unit itself according to a voltage difference between the non-inverting and inverting input signals, which is withstood by a MOS transistor with high withstand voltage, thus allowing a source-drain voltage of the input transistor pair to be within a voltage range accepted by process.

Abstract: A pulse width modulation circuit for an audio avoidance signal, which includes the circuit includes a power supply unit, a selection unit and a pulse width modulation unit; wherein the power supply unit includes a first voltage regulator and a second voltage regulator, which are respectively used to stabilize the system voltage and the bus voltage and output them alternately to the chip detection pin; the selection unit is used to divide the system voltage and the bus voltage, and output the selection voltage after comparing with the reference voltage, and the selection voltage controls the power supply unit and the pulse width modulation unit respectively; the pulse width modulation unit is used to receive the selection voltage of the selection unit, and realize the adjustment of the pulse width of the output signal based on the comparison of the enable signal.

Abstract: An oscillator circuit includes a frequency setting circuit, a first and a second clock signal generating circuit, a clock synchronization circuit, a control circuit, and an output circuit. The first and second clock signal generating circuits generate first and second clock signals respectively. The control circuit outputs a frequency setting signal via a second node, outputs the first clock signal via a sixth node, and outputs the second clock signal via a seventh node when the first frequency selecting signal is at an effective voltage level; otherwise, outputs a second synchronization control signal via the second node, outputs an external synchronization clock signal via the sixth node, and outputs a first clock signal via the seventh node. The clock synchronization circuit generates the first and second synchronization control signals. The output circuit outputs the first or second clock signal.

Abstract: A control circuit for a multi-phase power conversion circuit and a multi-phase power supply are provided. The conversion circuit includes a plurality of switching circuits which have output terminals being coupled together to supply power to a load. The control circuit includes an error amplifier, a pulse width modulation circuit, and a multi-phase logic control circuit. The multi-phase logic control circuit generates a plurality of PWM signals according to an on time signal, which are delayed phase by phase and control on and off states of the plurality of switching circuits, and each of which has a pulse width being consistent with the on time signal. This reduces the circuit size and cost of the multi-phase power supply controller, and solves the problem of phase-to-phase current oscillation in a case that the switching circuits operate under duty ratios independent for various phases.