Abstract: A field of memory technologies and a reading circuit for a differential one time programmable (OTP) memory including a first and second memory cells in a differentially symmetrical structure, the reading circuit connects between the first and second memory cells and includes: a detector having a first and second connected to respective first and second memory cells, configured to detect one of a resistance value of a first or second fuse of respective first and second memory cells, and a resistance difference between the first and second fuse after a burn-in operation of the first or second memory is completed; and a latch connected to the detector, provides a readout data according to one of the resistance value of the first or second fuse, and the resistance difference. The reading circuit may both read out data normally and detect a resistance value of the fuse.

Abstract: A one-shot circuit is provided. The one-shot circuit includes a one-shot main circuit and a shielding time window circuit. The one-shot main circuit is configured to receive, through a NOR gate, an input signal of the one-shot circuit, the feedback of an output signal of the one-shot circuit, and a time window signal output by the shielding time window circuit, and then obtain the output signal through a first RC delay circuit and a logic gate. The time window signal is a signal that resists the interference of the abnormal pulse of the input signal with the output signal. The shielding time window circuit is configured to receive the feedback of the output signal, and then obtain the time window signal through a second RC delay circuit and a logic gate.

Abstract: A battery protection chip, a polling detection method and a polling detection circuit based on a battery protection chip are provided. The circuit includes: a polling signal generator generating first and second selection signals based on a basic clock signal, a plurality of state signals and a priority of a plurality of detection items. An input array selector selects one of a plurality of reference signals and one of a plurality of feedback signals to output to a comparator based on the first selection signal; the comparator compares the feedback reference signals and outputs an indication signal. An output sampler samples the indication signal according to the second selection signal and updates the plurality of state signals according to a sampling result.

Abstract: Disclosed is a low dropout linear regulator including a power transistor and an error amplifier having a first input stage, a second input stage and a control circuit. The first input stage includes a first pair of transistors receiving an output voltage and a reference voltage, the second input stage includes a second pair of transistors receiving the output voltage and the reference voltage, the first and second pairs of transistors have different conductivity types. The control circuit controls turn-on and turn-off states of the first input stage according to the reference voltage, and turns on the first input stage when the reference voltage is less than a preset threshold, so that the error amplifier operates normally and the output voltage changes smoothly. When the reference voltage is greater than the preset threshold, the control circuit turns off the first input stage so that only the second input stage operates.

Abstract: Disclosed is a switching power supply circuit and a control circuit and a control method thereof. The control circuit comprises a control unit and a driving unit. The control unit controls the driving unit to provide a driving signal with different driving strengths according to a comparison result between a switching voltage and a preset voltage, so as to adjust a speed of turning the power switch off. By controlling the driving strength of the driving signal, a rising rate of the switching voltage can be improved, a spike of the switching voltage can be reduced, various components in the circuit can be protected from being damaged by the spike, and service life and reliability of the circuit can be improved.

Abstract: Disclosed is a low dropout linear voltage regulator and a control circuit thereof. The control circuit comprises an error amplifier, a foldback current-limiting protection circuit, an undershoot suppression circuit and an output detection circuit. The foldback current-limiting protection circuit limits the output current of power transistor and performs short circuit protection, the undershoot suppression circuit pulls the control terminal of the power transistor to low voltage level when the output voltage undershoots.

Abstract: A switching converter and a low-voltage startup circuit is provided. The low-voltage startup circuit includes a comparator and a substrate voltage control module. The comparator performs a comparison between an input voltage and a reference voltage and obtain a voltage detection signal according to a result of the comparison. The substrate voltage control module adjusts a substrate voltage of a main switching transistor according to the voltage detection signal, wherein when the voltage detection signal indicates that the input voltage is lower than/equal to the reference voltage, the substrate voltage control module increases the substrate voltage of the main switching transistor, and then a turn-on threshold voltage of the main switching transistor can be reduced, so that the main switching transistor may be normally turned on when the input voltage is low, and the low-voltage startup capability of the switching converter is improved.

Abstract: A single inductor positive and negative voltage output device, which not only reduces a chip area, but also meets mutual independent application needs of positive and negative voltage output load currents, which includes an inductor L, one end of the inductor L is connected to the drain of a first PMOS power switch M1 and to the drain of a third NMOS power switch M3 respectively, the other end of the inductor L is connected to the drain of a second NMOS power switch M2 and to the source of a fourth PMOS power switch M4 respectively, the gates of M1, M2, M3 and M4 are respectively connected to a drive circuit (1), the source of M1 is connected to a power supply terminal VIN, the source of M2 is connected to a ground terminal (6), the source of M3 is connected to a negative voltage output end VON, the drain of M4 is connected to a positive voltage output end VOP, the negative voltage output end VON is connected to ground terminal by a negative terminal capacitor CON, the positive voltage output end VOP is conne

Abstract: A single inductor positive and negative voltage output device, which not only reduces a chip area, but also meets mutual independent application needs of positive and negative voltage output load currents, which includes an inductor L, one end of the inductor L is connected to the drain of a first PMOS power switch M1 and to the drain of a third NMOS power switch M3 respectively, the other end of the inductor L is connected to the drain of a second NMOS power switch M2 and to the source of a fourth PMOS power switch M4 respectively, the gates of M1, M2, M3 and M4 are respectively connected to a drive circuit (1), the source of M1 is connected to a power supply terminal VIN, the source of M2 is connected to a ground terminal (6), the source of M3 is connected to a negative voltage output end VON, the drain of M4 is connected to a positive voltage output end VOP, the negative voltage output end VON is connected to ground terminal by a negative terminal capacitor CON, the positive voltage output end VOP is conne