Patents Assigned to SGS-ATES Componenti Elettronici SpA
  • Patent number: 4712127
    Abstract: A container for a semiconductor device has a metal plate and a body of synthetic resin which encapsulates a part of the plate, keeping a large surface thereof exposed. In the area separating the part encapsulated within the body of resin and the part without the resin, the plate has two opposed side notches and at least one groove connecting them.
    Type: Grant
    Filed: November 29, 1983
    Date of Patent: December 8, 1987
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Piero Colombo, Marino Cellai, Carlo Cognetti de Martiis
  • Patent number: 4638122
    Abstract: A telephone circuit which may be monolithically integrated, for generating control signals for displaying the telephone charges to a telephone user, is coupled to a AC voltage signal generator having a predetermined amplitude and frequency which are constant over time. The circuit includes a voltage generator for generating voltage signals which are spaced over time and have a trapezoidal pulse waveshape. A multiplier circuit calculates the product of the signals supplied by the two generators and supplies a signal which is sent to the speech circuit of the subscriber's line and is added to the speech (i.e.--conversation) signals. The circuit also includes a circuit for receiving an image signal of the overall signal adapted to the telephone line; a high-pass filter for eliminating the speech signal components from the image signal; a rectifier circuit for rectifying the filtered signal and a comparator for comparing the rectified signal with a reference signal.
    Type: Grant
    Filed: May 6, 1985
    Date of Patent: January 20, 1987
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Marco Siligoni, Ferdinando Lari, Vanni Saviotti, Vittorio Comino
  • Patent number: 4631561
    Abstract: A semiconductor suppressor device consists of a structure including a P-type substrate, an N-type epitaxial layer, a first P-type diffusion region in the epitaxial layer, and a second N-type diffusion region in the first region. A first metallic layer which is in contact with the substrate and a second metallic region which is in contact with the first and the second regions form the terminals of the device. The epitaxial layer has at least one zone along the junction with the first region which has a higher concentration than the rest of the layer so that the conduction through a reverse-biased junction occurs in this zone. This enables the establishment of a highly accurate striking potential for the suppressor device.
    Type: Grant
    Filed: July 23, 1984
    Date of Patent: December 23, 1986
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Mario Foroni, Franco Bertotti
  • Patent number: 4623950
    Abstract: A protective device for a power element of an integrated circuit includes a circuit element for detecting and processing the value of the current flowing through the power element and the voltage supplied to the power element. The circuit element generates a measuring signal which, when it reaches a predetermined limit value, activates a threshold circuit which reduces the current level in the power element. The protective device also includes a circuit element for amplifying the measuring signal when it reaches the predetermined limit value.
    Type: Grant
    Filed: January 30, 1984
    Date of Patent: November 18, 1986
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Sergio Palara, Aldo Torazzina
  • Patent number: 4612452
    Abstract: A control circuit for the switching of inductive loads which is monolithically integratable and includes an output stage having push-pull transistors. The base of each transistor of the output stage is connected to a driver circuit and to an auxiliary transistor which is biased in saturation. Each auxiliary transistor is driven to conduction in phase opposition with respect to the final transistor to which it is connected. The auxiliary transistor accelerates the turn-off of the final transistor, withdrawing the base charge, while delaying the turn-on thereof and absorbing the current fed thereto for a period of time equal to that of its own turn-off transient; in this way, the simultaneous conduction of the transistors of the final stage during the switching thereof can be avoided.
    Type: Grant
    Filed: March 17, 1983
    Date of Patent: September 16, 1986
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Fabrizio Stefani, Carlo Cini, Angelo Alzati
  • Patent number: 4611162
    Abstract: A monolithic integrated voltage regulator consists of a multiplicity of regulator circuits connected in parallel to one another. These circuits have different dropouts and the voltage established across each set of output terminals is held at a predetermined constant value by means of a regulator circuit having its feedback circuits connected thereto. The predetermined value of the voltage across one set of output terminals is deliberately selected to be more or less elevated according to whether the dropout of its associated regulator circuit is more or less elevated.
    Type: Grant
    Filed: June 12, 1984
    Date of Patent: September 9, 1986
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Pietro Erratico, Pietro Menniti
  • Patent number: 4563632
    Abstract: A monolithically integratable constant-current generating circuit includes a current-generating circuit having a control terminal and two output terminals, from which currents flow that are bound by a constant proportionality ratio.There is connected to one output terminal the input branch of a circuit having a current mirror and having a current gain which varies with the level of the current itself. A first input terminal of a current-comparator and amplifier circuit is connected to the output branch of the current mirror; a second input terminal is connected to the second output terminal of the current-generating circuit and the control terminal is connected to the output terminal of the current-comparator and amplifier circuit.
    Type: Grant
    Filed: September 21, 1983
    Date of Patent: January 7, 1986
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Sergio Palara, Bruno Murari
  • Patent number: 4555644
    Abstract: An output interface which includes a capacitor which is charged to a relatively high voltage by a voltage source which may have a high internal impedance, and a switching circuit which is controlled by an output of the associated logic circuit and which connects the capacitor with a gate electrode of a transistor of the final stage of the interface in order to bias it at a higher voltage than that of the power supply only during a prespecified logic state of the logic circuit and which keeps the capacitor essentially isolated (i.e.--floating) during any other logic state.
    Type: Grant
    Filed: December 12, 1983
    Date of Patent: November 26, 1985
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Daniele Devecchi, Guido Torelli
  • Patent number: 4553046
    Abstract: A bistable multivibrator circuit includes two main transistors and two other transistors and an additional pair of transistors. The multivibrator circuit can be monolithically integrated and has an output that can be placed in a preferential state. The two other transistors are utilized to set and reset the multivibrator circuit while the two additional transistors form a control circuit for controlling the multivibrator circuit so as to cause its outputs to be in a prescribed preferential state.
    Type: Grant
    Filed: May 26, 1983
    Date of Patent: November 12, 1985
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Angelo Alzati, Claudio Diazzi, Fabrizio Stefani
  • Patent number: 4507525
    Abstract: A transistorized bridge rectifier circuit with overcurrent protection which can be integrated monolithically is used for joining to a two-wire telephone line to the electronic circuits of a telephone subscriber set connected thereto. The circuit includes a transistorized bridge having a circuit arranged in the manner of a Graetz bridge. Rather than using separate elements for overcurrent protection, the circuit uses the bridge circuit elements themselves as protection elements. Diodes or diode connected transistors are respectively connected between the base and collector of transistors in two arms of the Graetz bridge and the resultant circuit thus provides overcurrent protection without the need of additional protection elements.
    Type: Grant
    Filed: January 25, 1983
    Date of Patent: March 26, 1985
    Assignee: SGS-Ates Componenti Elettronici SpA
    Inventors: Marco Siligoni, Nazzareno Rossetti
  • Patent number: 4417292
    Abstract: A protective current mirror, with a reflection ratio greater than one, is connected as the active load of an input differential amplifier of a power amplifier. This mirror is provided in addition to the usual current mirror which has its output connected to the drive transistor of the output power amplifier stage. The protective mirror senses the imbalance due to a voltage peak which occurs at an inverted input of the input differential amplifier at the very beginning of the descending portion of a sawtooth input signal ramp voltage and the protective mirror operates a protective transistor which is connected to the base of the power amplifier drive transistor so as to keep one power transistor of the final power amplifier stage in its inactive state. Protection of the output power transistor occurs before the output of the power amplifier has reached its maximum voltage level.
    Type: Grant
    Filed: May 13, 1982
    Date of Patent: November 22, 1983
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Valerio Borghese, Pietro Erratico, Silvano Coccetti
  • Patent number: 4059810
    Abstract: A metal plate carrying a semiconductive chip with a five-terminal power amplifier is encased in a prismatic resinous body having five tongues projecting from one side thereof, the central tongue being grounded to the plate while the other four are attached to various terminals of the chip. The projecting portions of the five tongues are alternately bent angularly in opposite directions to increase the separation of their free ends. During assembly, a connector strip bearing a number of five-tongue groups is fitted onto a support strip, divided into as many plate sections, by inserting a bent-over extremity of the central tongue of each group, provided with an enlarged head, into a recess of a confronting plate section preparatorily to encasement.
    Type: Grant
    Filed: March 29, 1976
    Date of Patent: November 22, 1977
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventor: Raimondo Paletto
  • Patent number: 4020807
    Abstract: In order to vary the timing of the ignition of an air/fuel mixture in a cylinder of an internal-combustion engine as a function of engine speed, a flip-flop is set by an engine-controlled switch at a predetermined point t.sub.0 in the cycle, in a position preceding by an angle .alpha..sub.0 the upper-dead-center position of an associated piston, to effect a rapid discharge and to start a slow recharge, at constant rate, of a capacitor C.sub.1 forming part of a time/voltage converter. The maximum voltage attained by this capacitor at the end of a cycle, as a measure of cycle length T, is registered in an ancillary capacitor C.sub.3 as another capacitor C.sub.2, forming part of a voltage/time converter, also begins charging at time t.sub.0 at a rate making the charges of capacitors C.sub.2 and C.sub.3 equal on or before the attainment of the UDC position. This equality is detected by a comparator which thereupon, at a time t.sub.0 +t.sub..gamma.
    Type: Grant
    Filed: January 16, 1974
    Date of Patent: May 3, 1977
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Giorgio Del Zotto, Mario Costa
  • Patent number: 3938053
    Abstract: A Class-B power amplifier, designed as a monolithically integrated circuit, comprises in its final stage an NPN output transistor Q4 whose base is driven by an NPN control transistor Q3 through the intermediary of a pair of current-replicating PNP transistors Q6, Q7 with interconnected bases having their emitters tied to the collector of the output transistor. Their common base lead, also tied to the collector of the replicating transistor Q6 to connect same as a diode, is joined to the collector of control transistor Q3; the collector of the second replicating transistor Q7 is joined to base of the output transistor Q4. An alternating signal is fed to the base of a PNP input transistor Q1 lying in series with a NPN pilot transistor Q2, the collectors of the two latter transistors being tied to the base of the control transistor Q3 whose emitter is connected to a load terminal jointly with the emitter of the output transistor Q4.
    Type: Grant
    Filed: September 19, 1974
    Date of Patent: February 10, 1976
    Assignee: SGS-ATES Componenti Elettronici SpA
    Inventors: Pietro Menniti, Bruno Murari