Abstract: A series voltage regulator having a regulating transistor (T.sub.1) arranged with its emitter-to-collector path in a series arm of the regulator, the base of which is controlled via a control transistor (T.sub.2) by a first differential amplifier (V) which compares a reference voltage (U.sub.REF) with a voltage proportional to the voltage (U.sub.2) of the regulator output. A differential circuit (V.sub.2) which compares the collector-to-emitter voltage of the regulating transistor (T.sub.1) with an auxiliary voltage (U.sub.3) is provided, the output of which is followed by a current limiting circuit (T.sub.3) which acts upon control transistor (T.sub.2). The auxiliary voltage (U.sub.3) is larger than the collector-to-emitter voltage of the regulating transistor (T.sub.1) which occurs at the beginning of the saturation state of the regulating transistor. The current limiting circuit (T.sub.3) limits the current delivered by the control transistor (T.sub.2) to the base of the regulating transistor (T.sub.

Abstract: A series voltage regulator having a regulating transistor (T.sub.1) arranged with its emitter-to-collector path in a series arm of the regulator, the base of which is controlled via a control transistor (T.sub.2) by a first differential amplifier (V) which compares a reference voltage (U.sub.REF) with a voltage proportional to the voltage (U.sub.2) of the regulator output. A differential circuit (V.sub.2) which compares the collector-to-emitter voltage of the regulating transistor (T.sub.1) with an auxiliary voltage (U.sub.3) is provided, the output of which is followed by a current limiting circuit (T.sub.3) which acts upon control transistor (T.sub.2). The auxiliary voltage (U.sub.3) is larger than the collector-to-emitter voltage of the regulating transistor (T.sub.1) which occurs at the beginning of the saturation state of the regulating transistor. The current limiting circuit (T.sub.3) limits the current delivered by the control transistor (T.sub.2) to the base of the regulating transistor (T.sub.

Abstract: A PLL circuit arrangement comprising a voltage controlled oscillator, the frequency of which is determined by the alternating charging and discharging of a capacitor, and a phase comparator, to a first input of which the output signal of the voltage controlled oscillator is supplied and to a second input of which a reference signal is supplied and from the output signal of which the signal controlling the oscillator is derived, wherein the capacitor can be charged by means of a current source circuit having a current intensity which can be switched over, the current intensity of the current source circuit can be switched over to a different value during each charging process, and wherein the moment of switching over of the current source circuit can be changed as a function of the output signal of the phase comparator.