Patents Assigned to SGS-Microelectronics S.r.l.
  • Patent number: 5617016
    Abstract: A DC-to-DC (buck) converter comprises a PWM regulation loop and a hysteretic control loop, which are alternatively enabled by a mode selection circuit of the converter in function of the load level. When the level of load drops below a preset limit related to a design load level, the converter passes from a PWM control mode to a hysteretic control mode, thus eliminating switching losses during periods of operation at relatively low load level.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: April 1, 1997
    Assignee: SGS Microelectronics, S.r.l.
    Inventors: Maria R. Borghi, Paolo Sandri
  • Patent number: 5606531
    Abstract: An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.
    Type: Grant
    Filed: March 31, 1995
    Date of Patent: February 25, 1997
    Assignee: SGS-Microelectronics, S.R.L.
    Inventors: Angelo Moroni, Flavio Scarra', Alberto Taddeo
  • Patent number: 5552731
    Abstract: A circuit for controlling a power transistor connected in series with a load. The circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, and which produces a signal at two levels referred to the node between the power transistor and the load. The level shifter includes a flip-flop the output of which controls the power transistor as well as two transistors driven by the control logic circuit to switch alternately and provide switching signals on the "set" and "reset" inputs of the flip-flop via two resistors. Two parasitic current generators inject current into the two resistors during the phase in which the power transistor is cut off. To prevent this current from causing unwanted switching of the flip-flop, a resistor connected to the "set" terminal of the flip-flop has a lower resistance than that of the other resistor.
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: September 3, 1996
    Assignee: SGS-Microelectronics S.r.l.
    Inventors: Claudio Diazzi, Fabrizio Martignoni, Mario Tarantola
  • Patent number: 5521439
    Abstract: A combination of an electronic semiconductor device comprising a metal plate and a plastics body which encapsulates the metal plate leaving at least a major surface thereof exposed, a heat sink, and means of fastening the heat sink to the device. To enable securement of the heat sink on the device without any external fastening arrangement having to be used, and without unduly straining the solder spot of the device pins to a printed circuit, the device is provided with undercut regions on opposite sides adjacent to the exposed surface of the plate for releasable engagement by the fastening means.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: May 28, 1996
    Assignee: SGS-Microelectronics S.r.l.
    Inventors: Paolo Casati, Giuseppe Marchisi