Abstract: A circuit for generating a signal with a 50% duty cycle comprises an oscillator that provides a first control signal, a reference generator that provides a first reference signal, a control circuit that provides a second control signal and that is responsive to the first reference signal, a first current source load inverter that provides the second reference signal and that is responsive to the second control signal, and an output circuit that provides an output signal having a duty cycle substantially equal to 50% and a frequency substantially equal to that of the first control signal. The output circuit further includes a second current source load inverter that is responsive to both the first and second control signals.

Abstract: A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.