Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided.

Abstract: An integrated device having an N-type well region formed in a P-type substrate and an N.sup.+ type contact ring housed in the well region. The well region forms respective capacitors with a conductive layer superimposed on the substrate, and with the substrate itself. The conductive layer and the substrate are grounded, and the contact ring is connected to the supply, so that the two capacitors are in parallel to each other and, together with the internal resistance of the well region, form a filter for stabilizing the supply voltage. When connected to an input buffer stage of the device, the filter provides for damping the peaks produced on the supply line of the input buffer by high-current switching of the output buffers.

Abstract: In a fully digital PWM controller employing a sine-triangle modulating technique, the method includes the step of linearizing the dependence of the selected scanning frequency of the memory containing the digital samples of the modulating sinusoid, from the value of the digital selection datum, and improves regulation at low speed by improving the resolution of selectable frequency values. The PWM driving signals produced by a fully digital controller implementing the linearization step of the invention show an F.F.T. extremely close to the F.F.T. of comparable PWM driving signals produced through a conventional analog technique.

Abstract: A process for fabricating an integrated memory matrix of EPROM cells having a "tablecloth" organization, with source and drain lines parallel among each other and running between parallel strips of isolating field oxide, floating gate structures formed between said source and drain lines and control gate lines running parallel among each other and perpendicularly to said source and drain lines and over said floating gate structures, utilizes a mask through which a stack, formed by a second level polysilicon layer, an interpoly isolating dielectric layer, a first level polysilicon layer and a gate oxide layer, is etched for defining in a longitudinal sense the gate structures (i.e. the channel length) of the EPROM cells. The gate structures are subsequently defined in a transversal sense by etching through another mask a stack comprising a third level polysilicon layer deposited directly over said second level polysilicon layer, said interpoly dielectric layer and said first level polysilicon layer.

Abstract: An audio amplifier having a low-noise input stage, being of a type which comprises a gain stage and an output stage cascade connected downstream from said input stage which includes first and second transistors having their respective bases connected to each other via corresponding input resistors, with the base of the first transistor also adapted to constitute a signal input for the amplifier, further comprises an electric connection between the collector of said second transistor and said input resistors to define a diode configuration for that second transistor, thereby the offset effect of the input resistors can be compensated for, and the noise voltage at the output from the amplifier downed.