Abstract: A merged power device structure, of the emitter-switching type, in which the emitter of the bipolar power transistor has a minimum-width pattern which is aligned to the trenches of a trench control transistor. Thus the current density of the bipolar is maximized, since the emitter edge length per unit area is increased. The parasitic base resistance of the bipolar can also be reduced.

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known.

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device.

Abstract: Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

Abstract: Testing of the gate oxides of all the transistors of a single die in a silicon wafer to be diced into a plurality of dice in a single operation is effected at an intermediate stage of the fabrication process by providing a metal layer contacting selectively each of the gate electrodes of a die at an intermediate stage of the processing and providing between the layer and the wafer a voltage of amplitude insufficient to cause significant tunneling current through good gate oxides but sufficient to cause significant tunneling current through defective gate oxides.