Abstract: The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.
Type:
Grant
Filed:
November 23, 1992
Date of Patent:
April 18, 1995
Assignee:
SGS-Thomson Micorelectronics S.r.l.
Inventors:
David Moloney, Gianfranco Vai, Maurizio Zuffada, Giorgio Betti, Fabrizio Sacchi