Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

Abstract: A method for forming a package of plastic material for a semiconductor electronic device having heat sink fully embedded within the package plastic case, is of the type which provides for forming the plastic case within a mold on whose interior a heat sink has been placed which has a first major surface to be insulated by means of a plastic material layer with a first thickness, whereon a metal leadframe and at least one semiconductor material die having an electronic circuit formed thereon have been fixed, and a second major surface opposite from the first and to be insulated by means of a plastic material layer with a second thickness, thinner than said first thickness; and at least one supporting element adapted to be positioned inside the mold cavity facilitating properly spacing the second surface of the heat sink out from a facing wall of the mold cavity during the process of introducing the plastic material for molding.

Abstract: Input-voltage-controlled pulse generator (VCO-PWM) for driving a pulse converter or switch-mode power supply with a variable duty ratio and a fixed maximum test level and variable clock frequency.

Abstract: A detection circuit for detecting the voltage between phases of a polyphase alternator for the purpose of controlling the putting into operation of a regulator for regulating the charging of a motor vehicle battery by said alternator, the circuit comprising differential discrimination means for the amplitude of the voltage between a pair of phase signals delivered by the alternator. The differential discrimination means comprise a pair of transistors each constituting means for comparing the inter-phase voltage with a threshold voltage defined by its emitter-base junction voltage, said threshold voltages being of small magnitude and of opposite polarity with respect to each other.

Abstract: A circuit for measuring current in a power MOS transistor (M0) comprises second (M1) and third (M2) transistors in series of the same type and same technology as, but having a smaller surface than, the power transistor and arranged in parallel on the latter. The two series transistors have their gates connected to the gate of the power transistor. The current in transistor (M2) which is connected to the reference electrode of the power transistor is measured.

Abstract: A limiting circuit comprises a comparator (B), which makes a comparison between the output voltage (Vc) of a power device and a predetermined reference voltage (Vrif). In the case wherein the output voltage is just below the reference voltage, the comparator supplies a current to the load (L) suitable for preventing the output voltage from falling further below the reference voltage.

Abstract: The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect to the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to and from the floating gate through an original self-aligned process, which allows limiting the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.

Abstract: The outer portion of a die stamped metal frame encompassing the outer ends of the electrical connecting pins is subjected to press striking for re-establishing planarity and parallelism of the opposite faces of the patterned pins which have become deformed during the die stamping, before proceeding to the assembly operations. The eventual bending of the pins of the finished product between a bending punch and a contrasting punch is performed on pins having planar and parallel faces thus preventing twisting and slanting of the bent pins.

Abstract: The disclosure concerns integrated memories and their redundancy circuits. The described redundancy concerns the memories organized in k groups of p columns (for example k=8 and p=64) to give words of k bits, when one column address out of p is chosen. The addresses of defective columns are memorized. In certain cases, the pad position (p0, p1, p2, p3) corresponding precisely to the defective column is also memorized. It is proposed to reduce the space occupied by the pad position determining logic circuits for which a redundancy has to be activated. This reduction is obtained by organizing a matrix EPROM to contain, for each defective column address, a memorized corresponding pad position. If there are N possibilities of repairs and r possible pad positions, the memory includes N lines and r columns. This is more than necessary, but that makes it possible to gain more space in avoiding the use of bulky logic decoders.

Abstract: The melting of a fuse of a CMOS type integrated circuit is caused by using the existence of a stray thyristor created in the neighborhood of the boundaries of pads made in a substrate. This stray thyristor is triggered by artificially making the potential drop in an intermediate region of the pad. The thyristor always comes on suddenly, the current that flows through the thyristor is very high and the phenomenon stops spontaneously when the fuse is melted.

Abstract: The disclosure concerns electrically programmable memories and, notably, the memories known as EPROMs, EEPROMs, FLASH-EEPROMs. To increase the information storage capacity of a memory, it is proposed to define at least three (instead of two) sections of current coming from a cell to which reading voltages are applied. These sections correspond to n possible programmed states of the cell. Comparators define a piece of information stored, for example, in two-bit form on the outputs S1, S2. However, to ensure safety during the reading despite programming uncertainties, the cell is tested by means of additional comparators and, if the cell current measured for a programming level defined among n levels is too close to the current threshold that defines the programming threshold at this level, an operation for complementary programming of the cell is triggered.