Abstract: An audio signal processor is disclosed which has at least one audio signal input and at least one audio signal output as well as at least one control input, and an audio signal processing unit connected between audio signal input and audio signal output, the audio signal processing unit having a programmable indicator tone generator circuit to be driven via the control input and whose indicator tone signal is switched to the audio signal output in accordance with the state of the control input.

Abstract: An electric signal processing circuit with an operational amplifier having a signal input, a feedback input and a signal output, and a nonlinear circuit device having a characteristic with a distortion-producing nonlinearity and located in the input signal circuit or in the feedback circuit of the operational amplifier, wherein a compensating circuit device having a characteristic with generally the same nonlinearity as the characteristic of the nonlinear circuit device is disposed in the feedback circuit or in the input signal circuit of the operational amplifier for compensating the distortion of the nonlinear circuit device.

Abstract: A method of phase synchronization of a bit rate clock signal generated on a receiver side with a biphase-modulated digital RDS signal that is demodulated on the receiver side with both signals having the same bit rate. The bits of both the RDS signal and the bit rate clock signal are each composed of two half bits having different digital potential values. The first or the second RDS half bit has a high digital value and the other RDS half bit has a low digital value based on which one of two logic values "1" and "0" is represented by the respective RDS bit. At a first time coinciding with the time of a rising and/or falling edge of a bit of the RDS signal, the digital value of the bit rate clock signal is measured as a first sample value, and at a second time shifted from the first time by a delay time that is shorter than a half bit duration, the digital value of the bit rate clock signal is measured as a second sample value.

Abstract: A controllable oscillator having a comparison unit, upstream of whose signal input an impedance converter is connected, and having two current mirror circuits which are provided as current sources and via which the oscillator frequency and the output impedance of the impedance converter are controlled. The range of adjustment of the oscillator frequency is expanded by the controlled output impedance.

Abstract: An integrated semiconductor circuit comprising an output terminal connected to a ground terminal via a series connection of a first switching transistor and a second switching transistor of inverse polarization with respect to the latter, each of said switching transistors having parasitic transistors. Whether the second semiconductor switch means is conducting or not, is dependent on the current flow through a resistor connected between gate and source of the second semiconductor switch means. Whether current flows through this resistor, is dependent on the switching condition of a further switching transistor, which in turn is also determined by the output signal of a comparator circuit by means of which a potential corresponding to the potential present at output terminal is compared to a reference potential.

Abstract: Circuit arrangement of a driver using bipolar NMOS technology for generating fast high/low edges with a low bias current requirement.

Abstract: A hysteresis comparator circuit using, for a virtually power-free detection of the voltage value to be subjected to a comparison, a differential stage utilizing on one end load transistors and on the other hand a negative feedback stage and preferably a current mirror stage. The control electrode of one load transistor is fed with the voltage to be used for the comparison. The control electrode of the other load transistor is fed with a reference voltage on the basis of which this load transistor forms a constant load impedance. The second load transistor has a third load transistor connected in parallel thereto, which in response to the output signal of the comparator is either conducting or blocking, so that in accordance with the output signal of the comparator, an additional load impedance is connected in parallel to the impedance of the second load transistor or no such connection is made.

Abstract: A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V.sub.S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator. (FIG.

Abstract: A method of assessing the quality and/or existence of a biphase-modulated digital RDS signal in a radio signal broadcast by a radio transmitter and received by a radio receiver equipped for RDS, in which a bit rate clock signal is produced on the receiver side whose bit rate is identical to that of the RDS signal, the bits both of the RDS signal and of the bit rate clock signal are each composed of two half bits, and of the two RDS half bits belonging to an RDS bit, one has a positive phase and the other one has a negative phase, and in which, for quality or existence assessment, the number of positive phase signs and the number of negative phase signs are determined which are each contained in the RDS signal during the half bit periods of a predetermined number of n adjacent half bits of the bit rate clock signal, and the RDS signal, depending on whether or not the ratio between the number of positive phase signs ascertained and the number of negative phase signs ascertained corresponds to a predetermined nu

Abstract: A comparator with hysteresis in bipolar technology having a voltage/current converter with a voltage input forming the comparator input connection, and a current output, a bistable current source with a current feeding connection coupled with the current output of the voltage/current converter and a current output connection forming the comparator output, the bistable current source being currentless in a first stable state and consuming current only in the second stable state, the firing current which must be fed to the current feeding connection to switch the bistable current source from the currentless state to the power-consuming state being different from the quenching current which must be fed to the current feeding connection to switch the bistable current source from the power-consuming state to the currentless state, to obtain a hysteresis of the comparator, and all transistors being formed as bipolar transistors.

Abstract: A driver circuit for an electronically commutated electric motor, in particular stepping motor, having one full bridge circuit (I, II) per motor winding (L1, L2), a current sensor resistor (R), a measured value storage device (C5) and a regulator circuit (OP1-OP5) for regulating, during part of the driver phases, the total current flowing through the driver circuit in such a way that this current matches a total current value flowing outside the regulating phases and stored in the storage circuit (C5), in order to prevent alternating components in the total current fed via the supply voltage lines.

Abstract: A method of and an apparatus for phase synchronization of a bit rate clock signal generated in an RDS receiver with a digital RDS signal demodulated on the receiver side, in which both the bit rate clock signal and the RDS signal have the same bit rate. Upon turning on of the RDS receiver and/or switching over of the same to a transmitter receiving frequency different from that received so far, a control signal is generated which, upon occurrence of the next rising edge or, alternatively, of the next falling edge of the RDS signal, effects such a phase angle shift of the bit rate clock signal that the bit rate clock signal, starting from that occurrence, is in phase synchronism with the RDS signal.

Abstract: An electronic storage circuit for storing information, in particular switch control information for alternately switching circuit parts of integrated monolithic circuits, having two series connections inserted between the two poles of a voltage supply source each including an EPROM transistor and a MOS transistor, the control gates of the two EPROM transistors being connected jointly with a reference voltage source, and the gates of the two MOS transistors with the connection point of the EPROM transistor and the MOS transistor of the other series connection.

Abstract: A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V.sub.S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator.

Abstract: A circuit combining the functions of phase-sensitive rectifier and integrator uses an operational amplifier and capacitors. A control signal switches a capacitor in and out of a feedback loop containing a second feedback capacitor, resulting in a residual charge in the second feedback capacitor if there is a phase-difference between an input signal and the control signal. The invention may also incorporate an automatic offset compensation circuit by using additional switches and a second control signal. The capacitor that is switched in and out of the feedback loop is coupled to a compensation capacitor during periods when the capacitor is not being used for the phase-sensitive rectifier and integrator portions of the circuit. The circuit arrangement allows the use of long time constants in the integrator portion of the circuit.

Abstract: An overvoltage protection device for protecting the electrical system of a vehicle against overvoltages, the vehicle having an on-board wiring network connected to an electrical generator and having electrical devices connected thereto, includes a controllable switch for effectively short-circuiting the generator in case of an overvoltage condition. The switch includes a switching transistor connected in parallel to the generator. Evaluation circuitry connected to receive the generator voltage is provided for issuing a first evaluation signal when a predetermined overvoltage threshold is exceeded and for issuing a second evaluation signal when the generator voltage subsequently falls below a predetermined low voltage threshold. A memory is provided for receiving the evaluation signals and for controlling the switching transistor. The memory stores one of the received evaluation signals until receipt of the other evaluation signal.

Abstract: A device for digital aurally compensated loudness control of audio signals, comprising two fine-stepped resistor chains connected in a series connection which on one end is adapted to be acted upon by the audio signal to be attenuated and whose connection point has a correction impedence connected thereto, and comprising one coarse-stepped resistor chain which at one end receives the fine-attenuated audio signal taken off from one fine-stepped resistor chain and which has at least one feed-in terminal at a predetermined location along the coarse-stepped resistor chain into which is fed a fine-attenuated audio signal taken off from the other fine-stepped resistor chain. The output signal of the device is taken off from the coarse-stepped resistor chain.

Abstract: A method of demodulating a biphase modulated signal is implemented by first establishing a reference phase angle level. The biphase modulated signal contains a series of bits, each bit having first and second half-bits. The half-bits are represented by opposite phase angle levels. First and second phase angle levels correspond to the first and second half-bits respectively. After the levels associated with first and second half-bits are measured, the two levels are compared. A binary value is assigned to each pair of first and second half-bits based on the relationship of their respective levels. For example, a high phase angle level followed by a low level, can represent the binary value "1", and vice versa.

Abstract: A digital push-pull driver circuit comprising two output transistors which are alternatingly controlled into the conducting state by a data control circuit and to whose common connection point a load to be driven is connected. One slope steepness reducing, enable-dependent delay circuit each is connected between the control electrode of each of the two output transistors and the data control circuit. The output of each delay circuit is connected to an enable input of the respective other delay circuit. The delay times of the two delay members are at least as long as the width of the steepness-reduced pulse slopes in terms of time.

Abstract: A comparator comprising two differential input stages (Q1 to Q4 and Q5 to Q8) which are connected in parallel and fed by a common constant circuit source (Q.sub.B) whose current is passed either to both or only to the one or only to the other differential input stage, depending on whether the common-mode input voltage of the comparator is within, above or below a voltage range that is between the voltage values of the two poles (VC, VE) of a supply voltage source (B) of the comparator, and comprising a common current mirror circuit (Q9, Q10) which is associated with the outputs of both differential input stages and from which the comparator output signal is derived. At least one (Q1 to Q4) of the two differential input stages operates in common-base connection, with this differential input stage (Q1 and Q4) receiving its supply current from the common-mode input voltage source.