Abstract: A computer instruction supply system has store and fetch circuitry for obtaining a sequence of instructions, test circuitry for locating the first instruction in the sequence to be enabled, and for testing separately successive instructions in the sequence to locate any branch instruction which is predicted to be taken and control circuitry to disregard target addresses of branch instructions in the sequence prior to the first instruction to be executed.

Abstract: A semiconductor device comprising a silicon substrate, an oxide layer on the silicon substrate, a doped polysilicon region disposed on the oxide layer, a dielectric layer which has been deposited over the doped polysilicon region and the silicon substrate, a contact hole which is formed in the dielectric layer and extends over respective laterally adjacent portions of the doped polysilicon region and the silicon substrate and a contact which has been selectively deposited in the contact hole which electrically connects the said portions together.

Abstract: An output driver circuit comprises a plurality of parallel pull up and pull down circuits each comprising at least one transistor switch switchable between on and off states and circuitry operable to maintain a desired resistance in the circuit when the transistor switch is switched on, and switch actuating circuitry including time delay circuitry for effecting a sequence of transistor switching operations in said pull-up and pull-down circuits with a time delay between successive operations, each operation effecting simultaneous switching of a transistor in one pull-up circuit and one pull-down circuit, whereby the output impedance is stabilised during a change in signal on the output terminal.

Abstract: The present invention proposes a method of manufacturing a ball grid array printed circuit board (210) that comprises the following steps: fabricating a printed circuit board, PCB, that comprises a matrix of ball grid array PCBs, each ball grid array PCB of the matrix is separated from its neighbors by the width of an electroplating tie bar (230); stamping the matrix of ball grid array PCBs for separating them and for forming an aperture (320) that is substantially centralized within each of them; preparing a metal sheet (510), onto which a semiconductor device (130) is mechanically attached; mechanically attaching a singularized ball grid array PCB to the metal sheet; and molding about the semiconductor device and a portion of the ball grid array PCB a protective material (140) that is substantially planar with respect to the ball grid array PCB.

Abstract: A computer and a method of operating a computer is disclosed which allow manipulation of data values in the context of the execution of so-called "packed instructions". Packed instructions are carried out on packed operands. A packed operand comprises a data string consisting of a plurality of sub-strings, each defining a particular data value or object. The invention relates to a restructuring instruction which allows objects to be reorganised within a data string thereby minimising loading and storing operations to memory.

Abstract: A pulse generator for use in generating pulses at different locations within a circuit has a first circuit 501 for a time dependent operation after receipt of a first input pulse and a second circuit 502 for carrying out a time dependent operation after receipt of a second input pulse after the first input pulse. A third circuit 503 is responsive to each of the first and second circuits 501,502 reaching respective predetermined conditions so that an output pulse is produced by the third circuit 503 at a time dependent on the average durations of operation of the first and second circuits 501 and 502.

Abstract: A oscillator having two synchronized oscillator rings is described. Synchronization is accomplished by circuitry connected between the outputs of two aligned stages in coupled oscillator rings, the circuitry being operable to maintain outputs of the stages 180.degree. apart in phase.

Abstract: A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage.

Abstract: A method of fabricating a semiconductor device incorporating a via and an interconnect layer of aluminium or aluminium alloy. The invention provides a semiconductor device including a via and an interconnect layer of aluminium or aluminium alloy, a capping layer of electrically conductive material which has been formed over the interconnect layer and an electrically conductive contact which has been selectively deposited on the capping layer thereby to form a via, the materials of the capping layer and of the contact being selected whereby at the interface therebetween there is substantial absence of non-conductive compounds formed from the material of the capping layer.

Abstract: An electrical assembly comprises an electrical component having an array of contact bumps. The component is mounted on a multilayer printed circuit board having a plurality of conducting pins located in holes in the board and having pointed ends projecting above the board and making electrical contact with the bumps on the component.

Abstract: A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match line for providing a signal to indicate when a match occurs between an input data word and data stored in a row of cells, which method comprises storing in at least one row of cells a data word in data cells of the row and a checking bit in said at least one additonal cell of the row, the checking bit having a value dependent on the content of the data word in accordance with an error checking system, and controlling a memory accessing system to effect an associate operation by inputting to the columns of cells an input word with an input checking bit dependent on said input word in accordance with the same error checking system, comparing the input word and input checking bit with stored contents of each row of cells and in any row where a mismatch of the i