Abstract: A threshold detecting device including a detecting stage having a first input supplied with a monitored voltage varying between a first and second value, a second input supplied with a reference voltage by a reference source stage, and an output supplying a logic signal indicating crossover of a predetermined threshold by the monitored voltage. Initially, the reference source stage is off and the reference voltage follows the course of the monitored voltage; upon the monitored voltage exceeding a first threshold value, the reference source is turned on and causes the reference voltage to rise more slowly than the monitored voltage, so that an increasing voltage difference is present between the first and second inputs of the reference stage; and, upon the voltage difference exceeding a second threshold value, the detecting stage switches and generates the threshold crossover signal.

Abstract: A power supply regulator comprising a regulated-voltage source; a buffer connected to the voltage source; and a diode connected to the output of the buffer. A bootstrap capacitor is located between the diode and the output of a power stage; and the output of the power stage is switched between a low and a high value by a digital signal also supplied to the input of the buffer which therefore generates a switched regulated output voltage varying between a first value equal to the regulated voltage and a second lower value. The switched regulated voltage switches from the first to the second value before the output of the power stage switches to high, thus immediately disabling the diode and preventing current spikes due to minority carriers in the diode from being transmitted to the regulated-voltage source.

Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells. The managing device comprises: at least one bidirectional internal bus for the transfer of data from and to the memory; a redundancy management line that is associated with the internal bus; means for enabling/disabling the transmission, over the internal bus, of the data from the memory toward the outside; means for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means for enabling/disabling the connection between the outside of the memory and the redundancy line during the reading of the memory matrix and during its programming.

Abstract: The present invention relates to a heat-dissipating and supporting structure for a semiconductor electronic device to be encapsulated within a molded plastic material package, of the type having an insulated inner heat sink. In particular, it comprises a heat-sink element which has a first largest surface to be insulated by means of a plastic material layer with a first thickness, and a second largest surface, opposite from the first, to be insulated by means of a layer of plastic material with a second thickness which is thin compared to the first thickness; and a leadframe consisting of a metal strip attached to the heat-sink element on the same side as the first largest surface and comprising a peripheral holder structure located outside the heat-sink element.

Abstract: The invention relates to a charge-pump control circuit for a power transistor including a driver circuit connected to a first supply voltage through a diode and to a second voltage through a switch and a first load. The driver circuit is connected to the power transistor, and the power transistor is linked to a pump capacitor. The power transistor is connected between a further supply voltage and a second load. The control circuit of the invention further includes a control logic circuit connected between the first supply voltage and the second voltage. The control logic circuit is connected to the driver circuit and to the switch, and the switch is connected between the power transistor and the first load. The switch is also connected to the driver circuit, and to a circuit for checking the charged state of the pump capacitor which is connected between the switch and the control logic circuit.

Abstract: Regulation of the output supply voltage to a load powered by a rechargeable battery of a portable apparatus, typically a telephone, is advantageously implemented by exploiting the switching STEP-DOWN REGULATOR of an in-built battery charger. The regulator circuit configures itself in function of the voltage level at the regulator input to retain an unmodified constant current and constant voltage battery charger function as long as a sufficiently high voltage source is connected to the input. Otherwise the battery voltage is applied to the input of the regulator and configuring means modify automatically the partition ratio of an output voltage sensing divider of the voltage-mode control loop of the charger, isolate the battery pole from the output and disable the current-mode control loop of the charger.

Abstract: A process for forming low threshold voltage P-channel MOS transistors in semiconductor integrated circuits for analog applications, said circuits including high resistivity resistors formed in a layer of polycrystalline silicon and N-channel MOS transistors having active areas which have been obtained by implantation in a P-type well, comprises the steps of,providing a first mask over both said resistors and the semiconductor regions where the low threshold voltage P-channel transistors are to be formed,doping the polycrystalline layer uncovered by said first mask,providing a second mask for protecting the resistors and the semiconductor regions where said low threshold voltage P-channel transistors are to be formed, andN+ implanting the active areas of the N-channel transistors.

Abstract: A process for the manufacture of an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well on a single-crystal silicon substrate; a step of formation of an active area on the surface of said N type well; a step of growth of a thin gate oxide layer over said active area; a step of implantation of a first heavy dose of N type dopant into said N type well to obtain an N type region; a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region to obtain an N+ contact region to both the N type well and said N type region; a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region to form a P+ region.