Abstract: A modular semiconductor power device has a conductive member consisting of an alumina plate to which copper layers are soldered on opposite sides. A chip is soldered to one of these layers and the other of these layers is soldered in turn to a metal heat sink. The chip is connected to respective copper strips which, in turn, are soldered to thermal strips originally forming part of a frame so that, after the device is encapsulated in a synthetic resin, the connecting members of the frame can be cut away to leave free ends of the latter strips exposed.

Abstract: A method of manufacturing memory cells is described, wherein the great selectivity of polysilicon etching with respect to oxide is employed for the elimination of the self-aligned polysilicon mask for the definition of the floating gate of the EPROM cell. In fact, according to the invention, the mask for the formation of the source and drain regions of one of the CMOS transistors is used for the removal of the oxide separating the two layers of polysilicon on the active region defining a memory cell, and the mask for the formation of the source and drain regions of the other CMOS transistor is employed for the removal of the lower layer of polysilicon around the floating gate of the memory cell, wherein the silicon portions which are not to be removed are covered by oxide.

Abstract: The integrated structure is formed of various circuital components accomplished by diffusion of dopants in a semiconductor substrate. Each component is located inside a respective insulation recess electrically floating in relation to the substrate and the other components.

Abstract: A circuit for recirculating an inductive load's (L) discharge current through the driving power switching transistor (Tpw) utilizes a control transistor (Tc) of opposite polarity to that of the power transistor and capable of withstanding a minimum fraction (1/.beta.) of the discharge current. The circuit has the advantage of allowing recirculation of current with a fixed overvoltage independent of the value of the supply voltage, without requiring additional power devices. The circuit may also be provided with means (D1, D2 and DZ1) to turn-on the control transistor in the presence of concomitant supply overvoltages to protect the power device from dumping effects.

Abstract: In this MOS-transistor bridge circuit, for obtaining a fast flyback conduction of the current after a normal operation of the circuit, instead of the flyback diodes associated with each transistor of the bridge, the MOS transistors themselves are employed, driven so as to conduct current from the ground to the power supply, that is in the opposite direction with respect to that of normal operation. For this purpose a control section is provided receiving at the input a fast flyback signal and comprising delay gates connected to the disable inputs of the transistors, so as to delay switching off thereof, and to maintain in the on state two diagonally opposed transistors so as to allow current to flow from the ground to the power supply through these diagonally opposed transistors and the load until the current decreases to zero.

Abstract: The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect of the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to an from the floating gate through an original self-aligned process, which allows to limit the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.

Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.

Abstract: The source is apt to generate a fully-differential reference voltage at the output terminals, whereto precisely-balanced loads are applied. The voltage reference is obtained from a bandgap voltage source fed with currents proportional to the temperature, in order to minimize thermal voltage variations. Suitable circuits for starting the normal source operation after switching on are also provided.

Abstract: The filter comprises four operational amplifiers in cascade, with switched capacitors in series at the input of every amplifier, with fixed capacitors in parallel to two of said amplifiers, with fixed and switched capacitors in parallel to the remaining amplifiers, and with fixed and switched capacitors in common to groups of several amplifiers in cascade. According to the invention, a path of fixed and switched capacitors in parallel connects the input of the filter to the input of the fourth amplifier, and a fixed capacitor connects the input of the filter to the input of the second amplifier.

Abstract: An integrated circuit for driving inductive loads comprises at least one substrate and a plurality of separate epitaxial wells, and has at least one output terminal for connection to an inductive load and a reference terminal for connection to a reference voltage. To reliably isolate the different epitaxial wells in each operating state, the circuit comprises diodes interposed between the substrate on one side and the output and reference terminals on the other to set the substrate to the reference potential when the potential on the output terminal is greater than the reference potential and to set the substrate to the output potential when the latter becomes smaller than the reference potential.

Abstract: A process for manufacturing CMOS devices is described, wherein two separate masks are used for the production of the gate regions of the two complementary transistors of the CMOS device, each of said masks allowing the formation of the gate region of only one of the two complementary transistors and being also used for the implantation of ions adapted to form the source and drain regions of said transistor. Accordingly only two masking steps are sufficient for the production of the gate, drain and source regions of the CMOS devices, with a reduction of the costs related to the production of integrated circuits executed in CMOS technology.

Abstract: A series voltage regulator includes a protective circuit that detects the collector current from a PBP power transistor and the collector-emitter voltage thereof. Such current and voltage signals are generated, respectively, by an auxiliary PNP transistor having a collector current which is proportional to that of the PNP power transistor, and by a circuit connected between the emitter and the collector of the PNP power transistor. The collector current and collector emitter voltage signals are processed by a circuit which, whenever the current and voltage values are greater than preset maximum values, reduces the PNP power transistor current and maintains it within permissible limits. The protective circuit does not affect the minimum voltage drop between the input and output of the regulator and may be dimensioned so as to use the maximum extent of the S.O.A. of the PNP power transistor.

Abstract: The invention concerns a process for manufacturing a monolithic integrated semiconductor device comprising an integrated control circuit and high-voltage power components. It solves the problem of undesired phantom layers created by out diffusion of the type-P dopant present in the insulation region of the substrate. Between a first epitaxial layer and a third epitaxial layer of the device, a second epitaxial layer is grown of predetermined thickness, and a first region for the insulation of the integrated control citcuit is formed in the first epitaxial layer and at least a second region for the buried layer is formed in the second eiptaxial layer.

Abstract: A container specifically designed for vacumm holding and shipping a silicon wafer, is provided with two circular portions having circumferentially, on bulged top and lower faces outer rasied edges and, within the top face of the circular portion forming the bottom portion of the assembled container, an inner edge.

Abstract: Latch-up in two supplies (+VCC and -VBB) CMOS integrated circuits is prevented by means of a single integrated protection MOS transistor, N-channel for P-Well CMOS or P-channel for N-Well CMOS, having its drain (source) connected to ground and its body region, gate and source (drain) connected to -VBB (+VCC). The desired threshold voltage and dimensions of the protection transistor do not present particular problems of implementation.

Abstract: In an amplifier stage comprising a pair of input current sources, connected in series between a pair of reference potential lines, a pair of output transistors connected between the pair of reference potential lines and defining an intermediate output terminal of the amplifier, a driving circuit comprising active elements and interposed between the input current source and the output transistors, and at least one saturation control circuit comprising at least one control transistor connected with its base to the driving circuit and with its collector and emitter between the output of the amplifier stage and the intermediate point between the input current sources, to detect distortion due to clipping, at least one distribution detection transistor is provided, connected to the control transistor so as to detect the current flowing through the latter, which current is related to the imbalance of the input current sources and therefore to the distortion generated in the stage.

Abstract: A CMOS power operational amplifier with large output voltage swing and high noise rejection is obtained by coupling a folded cascode type differential input stage and an output stage comprising an intermediate signal shifting amplifier and two common source output stages. Constant current generators inject into the drain of grounded gate MOS transistors pairs of said folded cascode type stage and of said intermediate signal shifting amplifier, respectively, a current which is pulled out of the source of the same grounded gate transistors by other constant current generators for increasing the effective transconductance of said grounded gate transistors pairs.

Abstract: An integrated circuit in a seven pin package particularly for audio signal amplification comprises at least two integrated amplifiers selectively commutable in a bridge configuration or in a stereo configuration by means of at least three integrated switches driven by an integrated comparator with threshold set by an internally generated reference voltage and whose input is connected to the SVR pin commonly used to implement the function of common mode signals rejections. The internal commutation between the two selectable configurations is obtained by varying the level of the bias voltage applied to said SVR pin by means of an external voltage divider.

Abstract: To obtain a constant quiescent current, high dynamics and high stability of a class AB output stage of low-frequency amplifiers, comprising an input transistor; a driving circuit comprising a current source, a first pair of driving transistors connected in series between the current source and the input transistor, a second pair of driving transistors mutually connected in series and driven by the first pair of driving transistors; as well as a pair of output transistors driven by the second pair of driving transistors, the driving circuit comprises a first resistor connected between the current source and the base of one of the first pair of driving transistors, a second resistor connected between the bases of the transistors of the first pair and a resistive network inserted in series between the transistors of the second driving pair.

Abstract: An electrically alterable, non volatile memory device capable of enduring a high number of cycles utilizes an array of "semidouble" cells, each formed by a pair of elementary EEPROM cells connected substantially in parallel and a single select transistor. A special program lines biasing circuit generating a bias voltage representative of a condition wherein one of the two elementary EEPROM structure is broken and sense amplifiers comprising a comparator circuit comparing the current flowing through an addressed semidouble memory cell with the current flowing through a reference cell comprising a pair of virgin EEPROM type elementary cells to ensure operability of each bit of the memory also when one of the two elementary cells supporting the bit fails. Different from known memories, only the EEPROM structure is duplicated while column lines, select lines and ancillary circuitry don't require duplication.