Abstract: A memory module without a controller and without a built-in power supply and a memory controller thereof are provided. The memory module includes a connection portion, a first non-volatile memory chip, and a second non-volatile memory chip. The memory controller of the motherboard accesses the first non-volatile memory chip by a native interface of the first non-volatile memory chip through the connection portion. The second non-volatile memory chip is configured to store at least one pointer of a meta data of the first non-volatile memory chip. The memory type of the second non-volatile memory chip is different from the memory type of the first non-volatile memory chip. The memory controller accesses the pointer stored in the second non-volatile memory chip through the connection portion.

Abstract: A memory module without a controller and without a built-in power supply and a memory controller thereof are provided. The memory module includes a connection portion, a first non-volatile memory chip, and a second non-volatile memory chip. The memory controller of the motherboard accesses the first non-volatile memory chip by a native interface of the first non-volatile memory chip through the connection portion. The second non-volatile memory chip is configured to store at least one pointer of a meta data of the first non-volatile memory chip. The memory type of the second non-volatile memory chip is different from the memory type of the first non-volatile memory chip. The memory controller accesses the pointer stored in the second non-volatile memory chip through the connection portion.

Abstract: A decoding method and device utilizing a flash channel characteristic and data storage system, wherein the method comprises: acquiring a probability density function curve diagram; determining a to-be-corrected data position according to the current situation of the probability density function curve diagram; transmitting the to-be-corrected data position to a low-density parity check module to perform an operation to correct the to-be-corrected value. The embodiment of the present invention considers the current situation of the probability density curve diagram when determining the to-be-corrected data position, namely, selects different solutions to determine the to-be-corrected data position on the basis of the current situation of the probability density function curve diagram, thus reducing the data transmitted to the low-density parity check module to perform an operation, and reducing operation workload and power consumption.

Abstract: Disclosed in an embodiment of the present invention are a hardware-based flash FTL function realization method and data storage device thereof, wherein the method comprises: when the data storage device is powered on, a state machine identifies the flash chip to acquire the chip information of the flash chip; the state machine establishes a target table according to the chip information; and the state machine realizes the FTL function of the flash controller according to the target table, wherein the FTL function comprises an address mapping function, a bad block management function and a garbage collection function.