Abstract: Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage.
Type:
Grant
Filed:
December 8, 2010
Date of Patent:
May 13, 2014
Assignee:
Shanghai Belling Corp., Ltd.
Inventors:
Zhengcai Qin, Qifu Liu, Nan Liu, Dajun Wu, Chengjie Zhou, Ning Lu, Ding Xu
Abstract: Provided is a level shift circuit which includes: a first level shift module; a first signal input terminal for providing a first input signal for the first level shift module; a first signal output terminal for providing output from the first level shift module; a second level shift module; a second signal input terminal for providing a second input signal for the second level shift module; a second signal output terminal for providing output from the second level shift module; a drive module connected to the first signal output terminal and the second signal output terminal; and a drive signal output terminal from the drive module. The level shift circuit of the present invention can be applicable for the requirements of BCD process and prevent damages to the high-voltage device due to the excessively high gate voltage.
Type:
Application
Filed:
December 8, 2010
Publication date:
September 26, 2013
Applicant:
SHANGHAI BELLING CORP LTD
Inventors:
Zhengcai Qin, Qifu Liu, Nan Liu, Dajun Wu, Chengjie Zhou, Ning Lu, Ding Xu