Abstract: The invention disclosed a method to make hard mask with ultra-small dimensions for fabricating integrated nonvolatile random access memory, for example, a magnetic-random-access memory (MRAM), a resistance random access memory (RRAM), a phase change random access memory (PCRAM), or a ferroelectric random access memory (FRAM). Instead of directly depositing hard mask material on top of the memory film stack element, we first make ultra-small VIA holes on a pattern transfer molding (PTM) layer using a reverse memory mask, then fill in the hard mask material into the VIA holes within the PTM material. Ultra-small hard mask pillars are formed after removing the PTM material. To improve the adhesion of the hard mask pillars with the underneath memory stack element, a hard mask sustaining (HMS) layer is added below PTM. Using PTM as the mask, array of HM ditches are first formed in the HMS layer to implant a hard mask seed in it before filling the main portion of the hard mask in the PTM VIAs.

Abstract: The invention discloses a magnetic random access memory (MRAM) storage element and a magnetic random access memory. The MRAM storage element has a stack structure formed by subsequently stacking a reference layer, a tunnel barrier layer, a first free layer, a perpendicular magnetic coupling layer, a second free layer, and a magnetic damping barrier layer. The magnetization vector in the second free layer is perpendicular to the film surface, and is parallel to the magnetization in the first free layer through parallel magnetic coupling to the first free layer. The perpendicular magnetic coupling layer is used to achieve a strong magnetic coupling between the first free layer and the second free layer and to provide additional interface perpendicular magnetic anisotropies for both the first free layer and the second free layer.

Abstract: A perpendicular STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a recording layer which has an interface interaction with an underneath dielectric functional layer. The energy switch barrier of the recording layer is reduced under an electric field applying along a perpendicular direction of the functional with a proper voltage on a digital line from a control circuitry; accordingly, the perpendicular magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A method of forming a magnetoresistive element comprises of forming a novel Boron-absorbing cap layer provided on the top surface of an amorphous CoFeB (or CoB, FeB) ferromagnetic recording layer. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the novel Boron-absorbing cap layer. Removing the top portion of the Boron-absorbing cap layer by means of sputtering etch or RIE etch processes followed by optional oxidization process, a thin thermally stable portion of cap layer is remained on top of the recording layer with low damping constant. Accordingly, a reduced write current is achieved for spin-transfer torque MRAM application.

Abstract: A magnetoresistive element comprises a novel Boron-absorbing cap multilayer provided on the top surface of an amorphous CoFeB (or CoB, FeB) ferromagnetic recording layer. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the novel cap layer. Removing the top portion of the cap layer by means of sputtering etch or RIE etch processes followed by optional oxidization process, a thin thermally stable portion of cap layer is remained on top of the recording layer with low damping constant. Accordingly, a reduced write current is achieved for spin-transfer torque MRAM application.

Abstract: This invention is about a method to make magnetic random access memory with small footprint directly on CMOS VIA with a self-aligned etching process. The process schemes of the method proceeds as: (1) Etch MTJ and BE using one or more of RIE and/or IBE processes with Ta as hard mask; (2) Etch BE using one or more of RIE and/or IBE processes with Ta & sidewall protection layer on MTJ as hard mask; and (3) Etch a part of MTJ and BE using one or more of RIE and/or IBE processes with Ta & sidewall protection layer on top portion of MTJ as hard mask. All the three schemes lead the BE to be self-aligned to MTJ cells, the photo overlay margin is not necessary and circuits could be made extremely small with lower manufacturing cost; The invention also provides schemes to prevent the electrical shorting across the tunnel barrier layer. Through trimming and sidewall protection deposition process, device performance and electrical/magnetic properties could be greatly improved.

Abstract: A magnetoresistive element has a crystalline structural quality and magnetic anisotropy enhancement bilayer (CSMAE bilayer) with a). enhanced the crystalline structural quality, hence fabrication yield, of the resulting magnetoresistive element; and b). enhanced the magnetic anisotropy of the recording layer whereby achieving a high MR ratio for the magnetoresistive element with a simultaneous reduction of an undesirable spin pumping effect. As the magnetoresistive film is thermally annealed, a crystallization process occurs to form bcc CoFe grains having epitaxial growth with (100) plane parallel to the surface of the tunnel barrier layer as Boron elements migrate into the impurity absorbing layer. Removing the top portion of the impurity absorbing layer by means of sputtering etch or RIE etch processes followed by optional oxidization process, a thin but thermally stable portion of impurity absorbing layer is formed on top of the magnetoresistive element with a low damping constant.

Abstract: A composite hard mask is disclosed that helps formation of an integrated circuit (IC), for example, a magnetic random access memory (MRAM) cell with ultra-small lateral dimension, especially 65 nm or finer ones. The hard mask element contains a heavy metal Ta layer and carbon layer atop the Ta. The IC or MRAM device pattern is first transferred from photoresist to carbon layer by ashing using gas(es) comprising oxygen, and then to heavy metal Ta layer using gas(es) comprising Fluorine. Alternatively, A dielectric layer selected from SiO2, SiN, SiON or SiC can be added atop the C layer to form a tri-layer hard mask element. By adding a thin dielectric layer above the carbon layer, the etching selectivity between photoresist and carbon layer can be further improved. Such a hard mask element is particularly needed for ultra-fine lithography including 193 nm lithography in which photoresist is thin and not sufficient to prevent a Ta layer from being etched away before a good hard mask is completely formed.

Abstract: This invention is about a method to make an MRAM element with small dimension, by building an MTJ as close as possible to an associated via connecting an associated circuitry in a semiconductor wafer. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.

Abstract: This invention is about a method to make an MRAM element with small dimension, by building an MTJ as close as possible to an associated via connecting an associated circuitry in a semiconductor wafer. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.

Abstract: Present invention includes an apparatus of and method of making a spin-transfer-torque magnetoresistive memory with three terminal magnetoresistive memory element(s) having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell has a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

Abstract: A planar STT-MRAM includes apparatus, made by a method of operating and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having a ferromagnetic recording layer forming a flux closure with a self-aligned ferromagnetic soft adjacent layer which has an electric field enhanced perpendicular anisotropy through an interface interaction with a dielectric functional layer. The energy switch barrier of the soft adjacent layer is reduced under an electric field along a perpendicular direction with a proper voltage on a digital line from a control circuitry; accordingly, the in-plane magnetization of the recording layer is readily reversible in a low spin-transfer switching current.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having a dielectric thermal buffer layer between a thin top electrode of the MTJ element and a bit line, and a bit-line VIA electrically connecting the top electrode and the bit line having a vertical distance away from the location of the MTJ stack. In a laser thermal annealing, a short wavelength of a laser has a shallow thermal penetration depth and a high thermal resistance from the bit line to the MTJ stack only causes a temperature rise of the MTJ stack being much smaller than that of the bit line. As the temperature of the MTJ element during the laser thermal annealing of bit line copper layer is controlled under 300-degree C., possible damages on MTJ and magnetic property can be avoided.