Abstract: The present application provides a method for making gates of different sizes compatible with the double patterning technology, comprising: forming a plurality of dummy gate structures and spacers on the sidewalls; covering the spacers and a region of large-sized gates with an SOC(silicon-on-carbon) layer; etching the SOC layer to expose the spacers of at least one dummy gate structure; respectively forming the first and the second SOC pattern structures, wherein the first SOC pattern structure covers the spacer of at least one dummy gate structure, and the second SOC pattern structure is disposed in region of the large-sized gates; etching the first SOC pattern structure to form a third SOC pattern structure, one side of the third SOC pattern structure covers one side of the spacer, wherein the other uncovered side of the spacer is used to define one side of the gate of medium-sized width.

Abstract: The present application discloses a method for making an 8-transistor 2-port static random access memory, wherein an N LDD process for 6 transistors in a chip memory area uses an N LDD mask and a P LDD mask of an original storage unit, and source and drain areas of an N transistor of a read port is opened for ion injection when LDD is performed for a logic device in a chip logic area to complete an N LDD process for the N transistor of the read port, so as to adjust a threshold voltage Vt and a source-drain breakthrough current Ids of the N transistor of the read port, thereby adjusting the read current and read speed for the read port without affecting the read/write balance for 6T SRAM inside a storage unit and without an extra mask or an increase in process steps.

Abstract: The present application provides a method for reducing a loss of a dielectric layer in an IO silicon oxide removal process, a plurality of gate structures arranged on a silicon bulk and spaced apart from each other, and an IO silicon oxide layer located between the bottom of the gate structure and the silicon bulk; depositing an etch stop layer; the gate structure being composed of a polysilicon structure, a first hard mask layer, and a second hard mask layer stacked from bottom to top; depositing a first dielectric layer to fill a space between the gate structures; performing etch back of the first dielectric layer; depositing a silicon nitride layer to continuously cover an upper surface of the first dielectric layer and an upper surface of the exposed etch stop layer; depositing a second dielectric layer on the silicon nitride layer.

Abstract: The present application relates to a method for making silicon epitaxy of a FDSOI device, which includes the following steps: providing a semiconductor structure; sequentially forming a first etch stop layer and an etch reaction layer on a surface of the semiconductor structure; performing an etching operation to the etch reaction layer to form a sidewall structure respectively; filling a second etch stop layer in a space between the sidewall structures at the position of the trench; etching the sidewall structures and the first etch stop layer under the sidewall structures to form a groove structure; removing the second etch stop layer and the remaining first etch stop layer; enabling a silicon substrate at the positions of the trench and the groove structure to epitaxially grow upwards to form epitaxial silicon, the epitaxial silicon being in flush with a top silicon layer.

Abstract: A method for making a semi-floating gate transistor with a three-gate structure is disclosed, comprising: forming a first trench structure in isolated active regions and a first polysilicon layer, removing part of the first polysilicon layer; forming a second gate oxide layer and a second polysilicon layer; patterning isolation trench; filling an isolation dielectric layer in the isolation trench; and forming a trench between two first trench structures, to cut open the second polysilicon layer, the second gate oxide layer, the first polysilicon layer and the first gate oxide layer into two parts, so that the active region is exposed from the bottom of the trench, wherein the first polysilicon layer on either side of the trench forms a first gate, and portions of the second polysilicon layer on both sides of the isolation trench form a second gate and a third gate.

Abstract: The present application discloses a method for manufacturing shallow trench isolation, comprising: step 1: performing first time etching on a semiconductor substrate by means of a dry etching process to form the shallow trench, wherein in the first time etching, metal ions are released from a dry etching process chamber and deposited on the inner surface of the shallow trench, and the metal ions diffuse and form a contamination layer; and step 2: performing second time etching on the semiconductor substrate exposed on the inner surface of the shallow trench by means of a wet etching process to remove the contamination layer on the inner surface of the shallow trench. In the present application, the metal ions released from the dry etching process chamber and deposited on the inner surface of the shallow trench during the dry etching of the shallow trench can be removed.

Abstract: The application provides a method for growing multiple layers of source drain epitaxial silicon in an FDSOI process, forming a buried oxide layer on the substrate, and then forming an SOI layer on the buried oxide layer; forming a gate on the SOI layer, wherein a source drain region is provided on two sides of the gate; forming an undoped epitaxial layer on the SOI layer of the source drain region; forming a first doped epitaxial layer on the undoped epitaxial layer; forming a second doped epitaxial layer on the first doped epitaxial layer; and cleaning the substrate with deionized water. In the present application, the epitaxial silicon is changed from a single layer structure to a multilayer structure, wherein undoped epitaxial silicon can effectively prevent ion diffusion, and middle-highly doped epitaxial silicon and highly doped epitaxial silicon can significantly reduce source drain resistance and improve device performance.

Abstract: The application discloses a method for forming a hybrid substrate of a SOI wafer. Buried oxide and silicon-on-insulator in some areas are removed, a layer of SiOCN is deposited on a SOI sidewall to protect the silicon-on-insulator sidewall, and then the growth of epitaxial silicon is performed to cause the silicon substrate area to grow to be flush with the silicon-on-insulator area. The SiOCN on the SOI sidewall acts as a protective layer to prevent the growth of epitaxial silicon on the SOI sidewall, thereby preventing the generation of a bulge at a boundary between the SOI area and the silicon substrate area and improving the product yield. Moreover, a SiOCN film may be deposited with high conformality, and the SiOCN deposited on the SOI sidewall has good uniformity, so that the growth of epitaxial Si from the SOI does not occur during subsequent growth of the epitaxial silicon.

Abstract: A method of failure analysis for locating open circuit defect in a metal layers, comprising: providing a chip sample having a metal layer, with an open circuit defect; delaminating the chip to expose the metal layer; depositing a metal conductive layer on the metal layer; removing a portion of the metal conductive layer to expose the metal layer; depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer; preparing a TEM slice sample which comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer; performing a VC analysis on the TEM slice sample to determine the defect position of the open circuit defect; and analyzing the defect position of the open circuit defect.

Abstract: The present application discloses a multi-level voltage detector circuit. The voltage dividing circuit includes a first resistor string and a second circuit. The first resistor string is formed by n+1 voltage dividing resistors connected in series and outputs n divisional voltages. The second circuit provides n lower voltage dividing resistors. A kth lower voltage dividing resistor detects kth rise and fall detection points of a power supply voltage. When the kth rise detection point is detected, the second circuit provides a kth lower voltage dividing resistor and short-circuits the kth lower voltage dividing resistor. When the kth fall detection point is detected, the second circuit provides the kth lower voltage dividing resistor to a position between a second end of an nth voltage dividing resistor and the ground. As the value of k increases, the resistance of the kth lower voltage dividing resistor decreases.

Abstract: The present application discloses a wet clean apparatus for a single wafer, comprising: a baffle arranged on the periphery of the wafer bearing platform. The anti-splash structure comprises: a first vertical plate, wherein a length direction thereof is perpendicular to the surface of the wafer; a first opening transversely passing through the first vertical plate, wherein the first opening is arranged on a movement track of the etchant shaken off from the surface of the wafer; and a second transverse plate, wherein a first end thereof is fixedly arranged on the outer side surface of the first vertical plate, the top surface of the second transverse plate is horizontal and is lower than or flush with the bottom surface of the first opening, and the etchant passing through the first opening flows on the top surface of the second transverse plate and is decelerated.

Abstract: The present application discloses a dose mapper method, which includes: step 1: collecting critical dimension fingerprint of each tool and each mask and storing the critical dimension fingerprint in a database; step 2: before exposing a wafer, pre-selecting the tool and the mask to be used, selecting the corresponding critical dimension fingerprint from the database and combining the corresponding critical dimension fingerprint to form total critical dimension fingerprint; step 3: obtaining dose mapper data for exposure of the wafer according to the total critical dimension fingerprint; step 4: exposing the wafer, and correcting the exposure of the wafer according to the dose mapper data in an exposure process. The present application can quickly and easily generate a dose mapper data file, especially when there is a new tool or mask to be expanded, thus improving the efficiency of generating the dose mapper data file and improving the production capacity.

Abstract: This application discloses a CIS pixel readout structure. An SF and an SG adopt an asymmetric spacer structure, so that the pitch from a lower end of a source metal plug of the SG to SG gate poly can be reduced while keeping the pitch from a lower end of a drain metal plug of the SF to SF gate poly unchanged, thus reducing the pitch from a drain connecting point of the SF to a source connecting point of the SG. Since a source of the SG is not connected with working voltage and it is not influenced by leakage, not only can GIDL current be maintained, but also parasitic resistance can be reduced. Without changing its effective size, it can reduce the parasitic resistance effect while reducing the area of a combined structure of the SF and the SG.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: The present application discloses a method for manufacturing a metal gate of a PMOS, comprising: step 1, forming a P-type work function metal layer; step 2, depositing an N-type work function metal layer by means of a PVD process, wherein over a bottom surface of a gate trench, the N-type work function metal layer has a hill profile; step 3, forming a first top barrier metal sublayer by means of a conformal growth process, wherein the first top barrier metal sublayer completely fills a sharp corner area of the N-type work function metal layer at a corner of the gate trench; step 4, growing a second top barrier metal sublayer by means of a PVD bombardment process; step 5, forming a third top barrier metal sublayer and a fourth top barrier metal sublayer; and step 6, forming a metal conductive material layer.

Abstract: The present disclosure discloses a method for manufacturing a NOR flash. The drain area groove and the peripheral isolation grooves are first formed and filled with the trench isolation oxide, followed by the formation of the source area groove, and then the SiH4 layer is deposited. Due to the poor filling property of SiH4, the air gap may be formed at the source area groove with a small gap, and at this time, the drain area groove in the drain area of the storage area and the peripheral isolation groove in the logic area both have been filled and thus are unaffected. The method for manufacturing a NOR flash of the present disclosure allows the formation of the source air gap of the NOR flash based on a post-source preparation process and good filling of the drain, reducing the coupling effect between the source polysilicon gates.

Abstract: The present disclosure discloses a polysilicon gate etch method, wherein base on the property that bombarding a photoresist with a HBr plasma cloud can cause a qualitative change in bonding energy of the photoresist, a linewidth cure step using only HBr is added to a polysilicon gate etch process. An injection flow rate of an HBr gas in the linewidth cure step is adjusted according to the needs of process integration, to reduce a linewidth difference between different polysilicon gate structures, thereby optimizing and quantifying post-etch critical dimensions of the polysilicon gate structures of different sizes. Accordingly, the problem of an unchangeable linewidth difference between different polysilicon gate structures after polysilicon etch in case of current fixed mask and lithography condition may be solved.

Abstract: The present application provides a method and a structure for improving ESD performance of a metal-gate high-voltage device, wherein a first STI region and a second STI region are formed within the high voltage P-well; a first high-voltage region N-diffusion region is formed within the high voltage P-well between the first STI region and second STI region; the area immediately adjacent to the first STI region and the area immediately adjacent to the second STI region are filled with silicon oxide; the silicon oxide immediately adjacent to the first STI region is formed as a first silicon oxide structure, and the silicon oxide immediately adjacent to the second STI region is formed as a second silicon oxide structure; and an IO N-well is formed within the first high-voltage region N-diffusion region of the lower area between the first silicon oxide structure and second silicon oxide structure.

Abstract: The present application provides a method for manufacturing a metal gate, comprising: step 1: forming a polysilicon dummy gate on a semiconductor substrate; step 2: forming low dielectric constant sidewalls, comprising: step 21: forming a first protective layer; step 22: forming a second low dielectric constant layer; step 23: forming a third protective layer; and step 24: performing blank etching, and forming the low dielectric constant sidewalls by stacking the first protective layer, the second low dielectric constant layer, and the third protective layer on the side surfaces of the polysilicon dummy gate; step 3: forming a zeroth interlayer film; and step 4: performing gate replacement, comprising: step 41: removing the polysilicon dummy gate, and forming a gate trench; and step 42: forming a metal gate in the gate trench.

Abstract: The present application provides a method for avoiding a damage to an overlay metrology mark, forming a plurality of raised silicon structures on an active area of a scribe line area on a silicon substrate, forming first to third dielectric layers on the silicon structure, and forming an axial structure of a fin and a spacer on the first to third dielectric layers; forming a shallow trench isolation (STI) area on the silicon substrate between the axial structures; removing a portion of the silicon structure along the height thereof on the scribe line area, the height of the residual silicon structure is 150-300 angstroms higher than that of the STI area; forming a plurality of dummy gates on the residual silicon structure on the scribe line, then applying a dielectric layer to fill a gap between the dummy gates, polishing the dielectric layer to expose the top of the dummy gate.