Abstract: The present invention provides an analysis method for a semiconductor device for analyzing a plurality of electrical parameters of a HKMG fin field effect transistor and a plurality of process parameters for manufacturing the transistor, comprising: performing key process parameter correlation analysis for each electrical parameter, wherein the key process parameter correlation analysis comprises: constructing multiple electrical-process models of the electrical parameter corresponding to each process parameter respectively; performing sensitivity analysis for each of the electrical-process models; determining a plurality of key process parameters from the plurality of process parameters based on the obtained sensitivity analysis results of the electrical-process models; and determining a relationship between the electrical parameter and the plurality of key process parameters based on a knowledge database.

Abstract: The present disclosure provides an ion implantation method and an ion implanter for realizing the ion implantation method. The above-mentioned ion implantation method comprises: providing a spot-shaped ion beam current implanted into the wafer; controlling the wafer to move back and forth in a first direction; controlling the spot-shaped ion beam current to scan back and forth in a second direction perpendicular to the first direction; and adjusting the scanning width of the spot-shaped ion beam current in the second direction according to the width of the portion of the wafer currently scanned by the spot-shaped ion beam current in the second direction.

Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Abstract: The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.

Abstract: The present disclosure provides a SONOS memory structure and a manufacturing method therefor. The SONOS memory structure including a substrate and a select transistor gate and a memory transistor gate formed on the substrate, wherein the substrate is a composite substrate including a base silicon layer, a buried oxide layer and a surface silicon layer, wherein the upper portion of the base silicon layer has a memory transistor well region formed therein; the select transistor gate and the memory transistor gate are formed on the surface silicon layer; the select transistor gate comprises a first select transistor gate and a second select transistor gate, the first select transistor gate and the second select transistor gate are respectively located at two sides of the memory transistor gate, and are electrically isolated from the memory transistor gate by first spacers on both sides of the memory transistor gate.

Abstract: The disclosure provides an ultra-low K dielectric layer and a manufacturing method thereof, the manufacturing method comprising: forming an ultra-low K dielectric layer on a substrate; forming a thin oxygen layer on the upper surface of the ultra-low K dielectric layer; performing plasma purge on the ultra-low K dielectric layer after forming the thin oxygen layer using oxygen; and the plasma purge lasts for more than 2 seconds. The ultra-low K dielectric layer manufactured according to the manufacturing method provided by the disclosure has a smooth surface, overcomes the original bump defects of the ultra-low K dielectric layer, and improves the performance of the ultra-low K dielectric layer. The manufacturing method of the ultra-low K dielectric layer provided by the disclosure has a simple process, is compatible with the manufacturing process of the existing ultra-low K dielectric layer, and has operability.

Abstract: The present disclosure provides an analysis method for a semiconductor device for analyzing a plurality of process parameters for manufacturing a HKMG fin field effect transistor. The analysis method specifically includes: establishing a plurality of process parameter models by grouping the plurality of process parameters in pairs; performing sensitivity analysis on each of the process parameter models; extracting a plurality of key process parameter models from the plurality of process parameter models based on the results of the sensitivity analysis; and performing data mining on the plurality of key process parameter models to determine a plurality of key process parameters and their correlations among the plurality of key process parameters. According to the analysis method provided by the present disclosure, related process parameters are highlighted by data mining and grouping, and the source of process parameter changes is explained. It is possible to adjust the process.

Abstract: The present disclosure provides an analysis method of a semiconductor device, and the semiconductor device comprises a plurality of HKMG fin field effect transistors and a wafer on which the plurality of HKMG fin field effect transistors are located, and the analysis method comprises: performing acceptance testing on the wafer to be tested; constructing an N-type model based on the position of each N-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, constructing a P-type model based on the position of each P-type transistor at the surface of the wafer to be tested and the corresponding acceptance test result, and constructing an N/P ratio model corresponding to the surface of the wafer to be tested based on the N-type model and the P-type model; and identifying the N/P ratio model based on a preset standard wafer model to determine whether the wafer to be tested is compliant based on the N/P ratio model.

Abstract: The present invention provides a method and apparatus for analyzing a semiconductor wafer for analyzing a defect distribution pattern on a semiconductor wafer to be tested. The method comprises: obtaining a defect distribution map of the semiconductor wafer to be tested, the defect distribution map indicating a defect distribution within a surface of the semiconductor wafer to be tested; establishing a three-dimensional model to be tested according to the defect distribution map, wherein an XY plane of the three-dimensional model to be tested corresponds to the surface of the semiconductor wafer to be tested, and a Z-axis of the three-dimensional model to be tested corresponds to the number of defects in each grid unit in the XY plane.

Abstract: The present disclosure relates to a circuit structure for in-memory computing. The circuit structure comprises a plurality of 8T SRAMs, four BLs, two WLs, and a direction configuration circuit. Each of the 8T SRAMs comprises two groups of read/write dual ports, two WL ports and two direction configuration ports. Data of first read/write port and second read/write port of each group of the read/write dual ports are inverse of each other. Each of the BLs is connected to a corresponding processor, and is connected to a read/write port of a corresponding read/write dual port of each 8T SRAM in a row direction or a column direction. Each of the WLs is connected to a corresponding processor and connected to a corresponding WL port of each 8T SRAM.

Abstract: The present invention provides a method for positioning short circuit failure, used to position the short circuit point between a first metal wire and a second metal wire. The positioning method comprises: measuring the resistance between the first metal wire and the second metal wire, and positioning the first region where the short circuit point is located by a resistance ratio. In the first region, the short circuit point may be gradually approached by periodically cutting the first metal wire and the second metal wire, electrically isolating the cut portions, and performing a plurality of voltage contrast analysis on the first metal wire and the second metal wire based on the principle of the dichotomy, thereby accurately locating the short circuit point. With the positioning method provided by the present invention, the region where the short circuit defect of the nA (nano ampere) level is located may be accurately found from the first metal wire and the second metal wire that are extremely long.

Abstract: The present disclosure relates to the field of semiconductor device etching process, and specifically discloses an etching method and a semiconductor device. The etching method comprises: providing a substrate on which a film layer to be etched is formed; forming a mask layer structure on the film layer to be etched, wherein the mask layer structure includes a dielectric layer formed on an upper surface of the film layer to be etched and an APF layer formed on an upper surface of the dielectric layer; patterning the APF layer; performing a first etching process on the dielectric layer and the film layer to be etched by using the patterned APF layer as a mask to pattern the dielectric layer and partially etch the film layer to be etched; removing the patterned APF layer.

Abstract: A failure positioning method for positioning leakage defect cell between the gate and the active region of transistor cells arranged in an array. The positioning method includes the steps of: measuring the resistance between a first metal wire connecting the active regions and a second metal wire connecting the gates, and positioning a first region where the defect cell is located by resistance ratio; electrically isolating the active region contact holes and the gate contact holes from each other; shorting the gate contact holes in the first region; and performing active voltage contrast analysis on the plurality of columns of transistor cells in the first region to position the leakage defect in the first region by comparing the voltage contrast images. With the positioning method, the transistor cell having a leakage defect at nA level may be accurately found from a plurality of transistor cells arranged in an array.

Abstract: The present disclosure provides an electric fuse structure and a manufacturing method therefor, the manufacturing method including providing a substrate, forming a polysilicon corresponding to the electric fuse structure on the substrate, performing a source-drain ion implantation of a first doping type on the polysilicon, performing a source-drain ion implantation of a second doping type on the polysilicon, the first doping type being different from the second doping type, and forming a metal salicide on the surface of the doped polysilicon. The electric fuse structure manufactured according to the manufacturing method provided in the present disclosure has a high post-value resistance, so that a programming current window is effectively optimized, and the manufactured electric fuse structure has a uniform internal interface and good electrical characteristics.