Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.

Abstract: The present invention disclosures a phase change memory unit, wherein comprising from bottom to top: a bottom electrode, a heating electrode, a phase change unit and a top electrode, the phase change unit is a longitudinally arranged column, which comprises: a cylindrical selector layer, a circular barrier layer and a circular phase change material layer form inside to outside; wherein, the bottom electrode, the heating electrode and the circular phase change material layer are sequentially connected, and the selector layer is connected to the top electrode. The present invention using trench sidewall deposition or via filling, forming the cylindrical phase change unit which is a circular nested structure, which can improve reliability of a device, greatly reduce volume of a phase change operation area and heat energy required, thus heating efficiency is improved obviously, the power consumption of the device is reduced, and high-density storage is realized.

Abstract: The present invention disclosures a recessed structure capable of being conveniently monitored online, wherein comprising a dielectric layer I, and a dielectric layer II positioned above the dielectric layer I, the dielectric layer I comprises a metal via layer and a metal contact layer, the metal contact layer is positioned above the metal via layer; the dielectric layer II comprises an inverted trapezoid groove positioned above the metal contact layer, the inverted trapezoid groove has inclined sidewall, and the horizontal cross-sectional area of the inverted trapezoid groove far away from the metal contact layer is larger than the horizontal cross-sectional area of the inverted trapezoid groove close to the metal contact layer; the inclined sidewall is covered with a reflective film.

Abstract: The present invention disclosures an image sensor structure and a formation method thereof, wherein comprising: a pixel unit array, a peripheral circuit set at the periphery of the pixel unit array, and a composite shield structure around the pixel unit array and between the pixel unit array and the peripheral circuit, the composite shield structure comprises a light shield structure and a heat shield structure; wherein, the light shield structure comprises a metal isolation structure around the pixel unit array for isolating light emitted by the peripheral circuit, and the heat shield structure comprises a cavity set inside the metal isolation structure, the cavity is filled with a thermal isolation medium for preventing heat transfer to the pixel unit array. The present invention can avoid image quality deterioration and distortion caused by light and heat of the peripheral circuit of the image sensor.

Abstract: The present disclosure provides a voltage conversion circuit and a chip. The voltage conversion circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor and a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a phase inverter; the source of the first PMOS transistor is connected to an I/O power supply, the drain thereof is connected with a first node, and the gate thereof is connected with a second node; the drain of the first NMOS transistor is connected with the first node, the source thereof is grounded, and the gate thereof is connected to an input signal.

Abstract: A memory and reading, writing and erasing methods thereof. The memory includes: H memory planes arranged in parallel along a first direction, where each memory plane extends in a second direction, and includes M columns of memory strings; each column of memory string extends in a third direction; the first direction, the second direction and the third direction are all different, and H and M are integers greater than zero; each column of memory string includes N rows of memristive memory cells. The memory is also provided with word lines, gating transistors, gating lines, bit lines and a common source line, where memristive memory cells in last rows of all memory strings are connected to the common source line, and the common source line is connected to a reference potential through a reference resistor. Use performance of the memory can be improved.

Abstract: The present invention provides a measurement system and modeling method for radio frequency MOS device modeling. Electrodes that are correspondingly provided in a slave test structure and a master test structure of the measurement system are different, where a source and a drain of a second MOS device are respectively connected to corresponding test ports, and a gate is independently connected out to facilitate setting a corresponding bias voltage. The modeling method configures an initial value of each parasitic element in a subcircuit model by means of a test result of the measurement system, corrects the initial values of at least some parasitic elements, and finally obtains parasitic parameter values of the parasitic elements.

Abstract: A clock circuit comprises an oscillator circuit and a power-on reset circuit, the oscillator circuit comprises a current generating module and a loop oscillation module connected together; the current generating module is used for outputting a control current to the loop oscillation module; the loop oscillation module is used for outputting an oscillation signal with a set frequency under action of the control current; and the power-on reset circuit is connected to the loop oscillation module and is used for providing an enabling control signal to the loop oscillation module after a power supply is powered on to the power-on reset circuit and the oscillator circuit.

Abstract: The present invention discloses a formation method, comprising: forming a hard mask layer and a photo-lithographic pattern of a fin structure on a the semiconductor substrate; patterning the hard mask layer and the semiconductor substrate to gain the fin structure with a profile of steep sidewalls; forming a protective layer on the sidewall surface of the fin structure; etching the semiconductor substrate located below the fin structure to form isolation structure trenches; performing a modified treatment on the exposed surfaces of the isolation structure trenches to form a modified layer with a certain thickness; removing the protective layer and the modified layer simultaneously; filling a dielectric layer in the isolation structure trenches till to cover the fin structure and then planarizing the dielectric layer; performing a trench etching to the dielectric layer and forming the fin structure and an isolation structure with sloped sidewalls.

Abstract: The present invention disclosures a Tip-to-Tip pattern preparation method, comprising: providing a substrate, and sequentially forming a layer to be etched, a first hard mask layer, a second hard mask layer, a sacrificial layer, a first dielectric layer and a first photoresist layer on the substrate, forming a first patterned photoresist layer which has a first Tip-to-Tip pattern by EUV lithography, and transferring the first Tip-to-Tip pattern to the second hard mask layer by etching; then forming a second patterned photoresist layer which has a second Tip-to-Tip pattern by the EUV lithography, and transferring the second Tip-to-Tip pattern to the second hard mask layer by etching; finally, transferring the first Tip-to-Tip pattern and the second Tip-to-Tip pattern to the layer to be etched.

Abstract: The present invention discloses a method for forming an intermetallic air gap, which comprises following steps: S01: forming a trench in a solid dielectric; S02: preparing an insulating sheet-like two-dimensional material, wherein the insulating sheet-like two-dimensional material comprises an insulating nano sheet-like layer, the size of the insulating nano sheet-like layer in the sheet-like two-dimensional direction is greater than the size of the trench; S03: the insulating sheet-like two-dimensional material is deposited on the solid dielectric and the trench; S04: annealing the solid dielectric and the insulating sheet-like two-dimensional material to form a stable thin film composed of insulating sheet-like two-dimensional material on the trench.

Abstract: The present invention discloses a pixel structure of a stacked image sensor and a preparation method thereof, by bonding processes to stack a first silicon wafer to a third silicon wafer up and down; wherein, a first photodiode array is set on the first silicon wafer located in middle, and a second photodiode array is provided on the second silicon wafer located above, and the surface of each the second photodiode in the second photodiode array is aligned and bonded correspondingly with the surface of each the first photodiode in the first photodiode array, so as to form a chip of the pixel structure of the stacked image sensor with a very deep junction depth, which is particularly suitable for near-infrared sensitization, and can effectively improve quantum efficiency in near-infrared wave bands; and by adopting a backlight technology, incident lights irradiating to photodiodes are not affected by the metal interconnect layers, both of sensitive and fill factor are high, especially for small-size pixels, whi

Abstract: The present invention discloses a bonding cavity structure and a bonding method, the bonding cavity structure comprises an upper carrier and a lower carrier, a gas-flow forming mechanism, which comprises multiple open-close integrated arms, the integrated arms are provided with multiple nozzles facing to wafer bonding surfaces, and the nozzles are switched to gas nozzles or vacuum suction nozzles, a closed space is formed by all the integrated arms closed together with the carriers, all the nozzle located on a side of two wafers are set as the gas nozzles, which blow gas parallel to the wafer bonding surfaces, meanwhile, all the nozzles located on the other side of the two wafers are set as the vacuum suction nozzles, which suck the gas blown from the gas nozzle at corresponding position, a high-speed gas-flow is generated between the two wafers, so as to produce a low pressure of Bernoulli effect, the wafers are not only subjected to thrust forces from backsides, but tension forces between the bonding surfac

Abstract: The disclosure discloses a CMOS image sensor, which includes a plurality of image sensor units and a resistance-to-digital converting unit. Each image sensor unit includes a pixel unit and a resistive random access memory unit connected to the pixel unit, the pixel unit is configured to convert a received optical signal into an analog signal and the resistive random access memory unit is configured to convert the analog electrical signal into a resistance value. The resistance-to-digital converting unit is connected to the plurality of the image sensor units, and is configured to convert the resistance value into a digital signal. The resistive random access memory unit is adopted in the present disclosure to replace a transistor device and is configured to convert resistance information of the resistive random access memory unit into a digital signal and output. Thus, digital quantization of image information is completed.

Abstract: The present disclosure relates to an image sensor structure and a manufacturing method thereof. A detection structure layer and a blind pixel structure layer are used. The detection structure layer and the blind pixel structure layer are effectively combined and further formed by ion implantation. Thus, the space ratio of a single pixel is reduced, the integration and device sensitivity are improved, and the blind pixel array and the pixel array are also in the same environment, thereby further improving the detection sensitivity and reducing the detection error.

Abstract: A transition metal dichalcogenide transistor, comprising: a gate, a gate dielectric layer and a channel layer from bottom to top, a source/drain region are located on both the sides of the gate dielectric layer, wherein, in a plane paralleled to the channel layer, the length of the channel layer in each direction is greater than the length of the gate dielectric layer, and the length of the gate dielectric layer in each direction is greater than or equal to the length of the gate; wherein, the source/drain region are a first transition metal dichalcogenide with metallic properties, and the channel layer is a second transition metal dichalcogenide with semiconductor properties.

Abstract: The present disclosure relates to an apparatus and a method for improving film thickness uniformity, wherein a PECVD machine with twin chambers comprise a wafer heating platform, which is set to be a rotating platform with programmable speed control, by setting rotating speed of the platform, wafer is rotated for integral rounds within process time, so that a RF overlap between the twin chambers make consistent influence on edge regions of the wafer, and film around the wafer is evenly distributed, which not only eliminate abrupt change of film thickness caused by the RF overlap, but also reduce film thickness differences between edge regions and central regions of the film by a characteristic that the RF overlap improves film deposition rate, so as to ensure the film thickness more evenly in the range of the whole wafer.

Abstract: A method of removing fixed pattern noise, comprising: S01: performing a single-frame segmented exposure on a pixel array; S02: reading a of the pixel array, comprising: S021: performing a soft reset, so as to set the reset signal of the pixel unit to an intermediate voltage, and reading a differential reset signal; S022: performing a hard reset so as to set the reset signal of the pixel unit to a high voltage; S023: turning on a transmission MOS transistor to enable an exposure signal of to photodiode to transmitted to the floating diffusion area, and reading a differential pixel transmission signal; S03: subtracting the differential reset signal from the differential pixel transmission signal to obtain an exposure signal with fixed pattern noise removed. Another method is removing fixed pattern noise and an image sensor are further provided.

Abstract: The present invention discloses an image sensor for real-time calibration of dark current, including a pixel array comprises at least a pixel unit, the pixel unit includes a pixel photosensitive portion, a pixel dark shielding portion and a subtraction circuit, photodiodes in the pixel photosensitive portion and the pixel dark shielding portion are isolated by deep trench isolations, the pixel dark shielding portion are covered by a dark shielding layer; both of the pixel photosensitive portion and the pixel dark shielding portion adopt a same voltage and sequential control, a light ambient voltage signal and a non-light ambient voltage signal are generated and connected to both ends of a subtraction circuit to realize subtraction and dark current calibration.

Abstract: The present disclosure provides an image sensor and a method for manufacturing deep trench and through-silicon via of the image sensor, wherein: providing a pixel silicon wafer, performing a silicon wafer thinning on a second side of the pixel silicon wafer; forming a deep trench on the the second side of the pixel silicon wafer; filling the deep trench with organic material; coating photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a through-silicon via according to the through-silicon via pattern; depositing a dielectric protective layer on the surface of the deep trench and the surface of the through-silicon via; filling the deep trench with organic material; coating the photoresist on the second side of the pixel silicon wafer; etching the second side of the pixel silicon wafer to form a contact hole according to the contact hole pattern, depositing a barrier layer on the surface of the deep trench and the surface of the through-silicon v