Abstract: The present invention provides a multi-system multi-band RFID antenna, which comprises an on-chip antenna and at least one external antenna, wherein the on-chip antenna is arranged on RFID chip; the external antennas are arranged outside the RFID chip; and the RFID chip is provided with connection pads on the outer surface, wherein both the on-chip antenna and the external antennas are connected with the RFID chip through the connection pads. According to the multi-system multi-band RFID antenna of the present invention, the RFID chip can provide appropriate antennas for applications in different systems with different frequency bands, and can satisfactorily meet the need for RFID multi-system integration applications in the future.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.

Abstract: The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.

Abstract: The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices.

Abstract: The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) material on the first photoresist pattern, promote thermal crosslinking reaction at the interface between the RELACS materials and the first photoresist pattern; afterwards, remove the RELACS material which does not crosslink with the first photoresist pattern. This method not only realizes higher lithography resolution, but also avoids the adverse effects of the second exposure on the first photoresist pattern in double-exposure technology.

Abstract: A semiconductor device includes a damascene structure and an air gap embedded in the damascene dielectric layer. A method of manufacturing a semiconductor device includes depositing a metal barrier in advance as an etch stop, forming a copper damascene interconnect structure, forming an air gap, and depositing a photosensitive passivation material on the air gap.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.