Abstract: Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

Abstract: The present disclosure provides a digital PCR system. The system includes a droplet formation assembly and a droplet orifice assembly. The droplet formation assembly includes a heat conducting plate and a cover plate, at least one inverted U-shaped step is placed on a side surface of the cover plate, the heat conducting plate, the cover plate and the inverted U-shaped step together form a droplet formation chamber having an opening at a bottom. The droplet orifice assembly is connected below the droplet formation assembly, and includes a plurality of droplet orifices, the droplet orifice is connected with the droplet formation chamber, and a vaporization component is placed in the droplet orifice, the vaporization component vaporizes a digital PCR solution in the droplet orifice and rapidly pushes the digital PCR solution into a droplet forming oil in the droplet formation chamber, to form a digital PCR droplet.

Abstract: Disclosed is a field-effect transistor and a method for manufacturing a field-effect transistor. The method comprises: forming an NMOSFET region and a PMOSFET region on a substrate; forming a hard mask on the NMOSFET region and the PMOSFET region, and patterning through the hard mask; forming a multiple of stacked nanowires in the NMOSFET region and a multiple of stacked nanowires in the PMOSFET region; forming a first array of nanowires in the NMOSFET region and a second array of nanowires in the PMOSFET region; and forming an interfacial oxide layer, a ferroelectric layer, and a stacked metal gate in sequence around each of the nanowires included in the first array and the second array. Wherein the NMOSFET region and the PMOSFET region are separated by shallow trench isolation.

Abstract: This present disclosure provides a microstructure and a method for manufacturing the same. The method includes: disposing a liquid film on a surface of a substrate, wherein a solid-liquid interface is formed where the liquid film is in contact with the substrate; and irradiating the substrate with a laser of a predetermined waveband to etch the substrate at the solid-liquid interface, wherein the position where the laser is irradiated on the solid-liquid interface moves at least along a direction parallel to the surface of the substrate, and the absorption rate of the liquid film for the laser is greater than the absorption rate of the substrate for the laser.

Abstract: The present disclosure provides a packaging method and a semiconductor device, the packaging method comprising: depositing a first sacrificial layer on a substrate to cover a semiconductor element formed on the substrate; covering a first dielectric layer on an upper surface and a side wall of the first sacrificial layer, the first dielectric layer has a first groove exposing part of the first sacrificial layer; covering a second sacrificial layer on surface of the exposed first sacrificial layer; covering a second dielectric layer on the second sacrificial layer and the exposed surface of the first dielectric layer, the second dielectric layer having a releasing hole exposing the second sacrificial layer and a second groove; depositing a filling layer to fill the second groove; by the releasing hole, removing the second sacrificial layer and the first sacrificial layer to form a cavity; depositing a third dielectric layer which covers the exposed surface of the second dielectric layer, and filling the releas