Abstract: A read-out circuit and a read-out method for a three-dimensional memory, comprises a read reference circuit and a sensitive amplifier, the read reference circuit produces read reference current capable of quickly distinguishing reading low-resistance state unit current and reading high-resistance state unit current. The read reference circuit comprises a reference unit, a bit line matching module, a word line matching module and a transmission gate parasitic parameter matching module. With respect to the parasitic effect and electric leakage of the three-dimensional memory in the plane and vertical directions, the present invention introduces the matching of bit line parasite parameters, leakage current and transmission gate parasitic parameters into the read reference current, and introduces the matching of parasitic parameters of current mirror into the read current, thereby eliminating the phenomenon of pseudo reading and reducing the read-out time.

Abstract: A nitrogen oxide gas sensor based on sulfur-doped graphene and a preparation method therefor. The method includes the following steps: 1) providing graphene and a micro heater platform substrate, and transferring the graphene onto the micro heater platform substrate; 2) putting the micro heater platform substrate covered with the graphene into a chemical vapor deposition reaction furnace; 3) performing gas feeding and exhausting treatment to the reaction furnace by using inert gas; 4) simultaneously feeding inert gas and hydrogen gas into the reaction furnace at a first temperature; 5) feeding inert gas, hydrogen gas and sulfur source gas into the reaction furnace at a second temperature for reaction to perform sulfur doping to the graphene; and 6) stopping feeding the sulfur source gas, and performing cooling in a hydrogen gas and insert gas shielding atmosphere.

Abstract: A phase-transition type vanadium oxide material and a preparation method therefor. The preparation method includes the following steps: providing a vanadium oxide base material, and implanting gaseous ions into the vanadium oxide base material, to obtain a phase-transition type vanadium oxide material having a preset phase-transition temperature. Subsequently, optionally, further annealing may be performed to adjust a bubble generation status in vanadium oxide after the gaseous ions are implanted, to further adjust the stress and strain and the phase-transition temperature. The method for preparing a phase-transition type vanadium oxide material consistent with the present invention has simple steps, desirable process reproducibility, high flexibility, and the phase-transition temperature of vanadium oxide can be continuously adjusted by changing an implantation dosage of the gaseous ions.

Abstract: An AlGaN/GaN HEMT based on fluorinated graphene passivation and a manufacturing method thereof. Monolayer graphene (108) is transferred to an AlGaN (104) surface, is treated by using fluoride ions and then is insulated to thereby replace a conventional nitride passivation layer. Then, a high-k material (109) is grown on the graphene (108), and the high-k material (109) and the graphene (108) are jointly used as a gate dielectric for preparing an AlGaN/GaN metal-insulator-semiconductor (MIS) HEMT. Compared with the traditional passivation structure, the graphene (108) has the advantages of small physical thickness (sub-nanometer scale) and low additional threshold voltage. The structure and the method are simple, the effect is remarkable and the application prospect in technical fields of microelectronics and solid-state electronics is wide.

Abstract: A read circuit of storage class memory comprises: an array; a read reference circuit, having the same bit line parasitic parameters as the array, having the same read transmission gate parasitic parameters as the array, used to generate a read reference current; a sense amplifier, providing the same current mirror parasitic parameters as the reference side, used to generate a read current from a selected memory cell, compare the said read current with the said read reference current and output a readout result. In the present invention, the said read current and the said read reference current are generated at the same time, the transient curve of the said read reference current is between the low resistance state read current and the high resistance state read current from an early stage. The present invention largely reduces the read access time, has a good process variation tolerance, has a wide application, and is easy to be used in the practical product.

Abstract: A phase change material for a phase change memory and a preparing method thereof. The phase change material for a phase change memory has a chemical formula of Sc100-x-y-zGexSbyTez, wherein 0?x?60, 0?y?90, 0<z?65, 0<100-x-y-z<100. The phase change material for a phase change memory according to the present invention is capable of repeatedly changing phases. The Sc100-x-y-zGexSbyTez has two different resistance value states, i.e., a high resistance state and a low resistance state, and a reversible transformation between the high resistance state and the low resistance state can be achieved by being applied a pulse electrical signal thereto, which satisfies basic requirements of a storage material for the phase change memory.

Abstract: An undulator comprises at least M permanent magnet periods arranged sequentially in a transmission direction of electron beams, each of the permanent magnet periods comprises four rows of permanent magnet structures, in which each row comprises N rows of permanent magnet groups, and each row of the permanent magnet groups comprises K permanent magnet units, wherein M, N and K are natural numbers greater than or equal to 1; the four rows of the permanent magnet structures are pairwise matched, then relatively disposed on both sides of the transmission direction of electron beams, and are capable of forming at least one composite magnetic fields by relative displacement, such that elliptically polarized light, circularly polarized light, or linearly polarized light with an arbitrary polarization angle of 0°˜360° is generated when electron beams pass through the composite magnetic fields, and such that velocity directions of electrons are deviated from an axis direction of the undulator.

Abstract: A nano-scale superconducting quantum interference device and a manufacturing method thereof, comprising the following steps of: S1: providing a substrate and growing a first superconducting material layer thereon; S2: forming a photo-resist layer and performing patterning; S3: etching the first superconducting material layer in a predetermined region; S4: covering a layer of insulation material on a top and a side of a structure obtained in step S3; S5: growing a second superconducting material layer; S6: removing the structure above the plane where the upper surface of the first superconducting material layer locates, to obtain a plane superconducting structure, in the middle of which at least one insulating interlayer is inserted; S7: forming at least one nanowire vertical to the insulating interlayer, to obtain the nano-scale superconducting quantum interference device. The width of the superconducting ring and the length of the nano junction are determined by the insulating interlayer.

Abstract: A phase change memory and its fabrication method are provided. A bottom electrode structure is provided through a substrate. A mask layer is formed on the substrate and the bottom electrode structure. A first opening is formed in the mask layer to expose the bottom electrode structure. A spacer is formed on sidewalls and bottom surface portions of the first opening to expose a surface portion of the bottom electrode structure. The first opening including the spacer therein has a bottom width less than a top width. A heating layer is formed at least on the surface portion of the bottom electrode structure exposed by the spacer. A phase change layer is formed on the heating layer to completely fill the first opening. A top electrode is formed on the phase change layer and the mask layer.

Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.