Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.

Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

Abstract: Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.

Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

Abstract: In one embodiment the present invention includes a method of fabricating a chip scale package (CSP). The method includes forming conductive bumps on a top side of a semiconductor wafer; mounting the top side of the semiconductor wafer on adhesive tape; sawing the semiconductor wafer a first time such that a wide sawing kerf is obtained; molding the semiconductor wafer with a molding compound; and sawing the semiconductor wafer a second time to obtain the CSPs. Such method has improved efficiency as compared to many existing methods of fabricating CSPs.

Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

Abstract: Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut.

Abstract: In one embodiment the present invention includes a method of manufacturing a chip scale package. Embodiments of the present invention include sawing kerfs between semiconductor device boundaries on opposite sides of the wafer and filling the kerfs with mold compound. The devices may then be sawed into individual packaged devices encapsulated in mold compound. In one embodiment, kerfs on opposite sides of the wafer have different widths to create a step in the wafer boundary with the mold compound, which improves the integrity of the package. In one embodiment, a device and one or more neighboring devices are bonded together using bond wires to form a group of device that are encapsulated in mold compound.

Abstract: In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. Such method results in improved quality of wire leads, improved lifespan of cutting blades, and reduction of burrs as compared to many existing methods of fabricating QFN chip packages.