Abstract: The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.

Abstract: A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.

Abstract: A surface oxidation method for a wafer, the method comprises: raising a temperature on the wafer in an oxidation atmosphere, the temperature is raised from a start temperature to a target temperature at a temperature raising rate greater than 5° C./min, the temperature is raised in a vertical furnace tube of an annealing furnace, the vertical furnace tube includes a gas intake conduit arranged on a side wall, the gas intake conduit includes a gas inlet arranged to be proximate to a bottom of the vertical furnace tube and a gas outlet arranged to be proximate to a top of the furnace tube, the wafer overlying the vertical furnace tube; and isothermally oxidizing the wafer at the target temperature in the oxidation atmosphere.

Abstract: A surface oxidation method for a wafer, the method comprises: raising a temperature on the wafer in an oxidation atmosphere, the temperature is raised from a start temperature to a target temperature at a temperature raising rate greater than 5° C./min, the temperature is raised in a vertical furnace tube of an annealing furnace, the vertical furnace tube includes a gas intake conduit arranged on a side wall, the gas intake conduit includes a gas inlet arranged to be proximate to a bottom of the vertical furnace tube and a gas outlet arranged to be proximate to a top of the furnace tube, the wafer overlying the vertical furnace tube; and isothermally oxidizing the wafer at the target temperature in the oxidation atmosphere.

Abstract: A method for planarizing a wafer surface comprising: providing a first wafer and a second wafer, oxidizing the first wafer to form an oxide layer on a surface of the first wafer, injecting a foaming ion to form a peeling layer in the first wafer, bonding the first wafer and the second wafer to form a bonded wafer by using the oxide layer as an intermediate layer, raising a temperature to cause the bonded wafer to crack in the peeling layer, a portion of the first wafer remaining on the surface of the oxide layer being a top silicon layer, and the oxide layer being an insulating buried layer, etching a surface of the top silicon layer with a mixed gas of hydrogen and HCl, wherein the mixed gas is injected from a side of the wafer, wherein a flow rate of the mixed gas in an edge region is less than a flow rate of the mixed gas in a central region.

Abstract: A method for planarizing a wafer surface includes the following steps: providing a first wafer and a second wafer, oxidizing the first wafer to form an oxide layer on a surface of the first wafer, injecting a foaming ion to form a peeling layer in the first wafer, wherein an injection depth of the foaming ion is subject to the thickness of the oxide layer, bonding the first wafer and the second wafer to form a bonded wafer by using the oxide layer as an intermediate layer, raising a temperature to cause the bonded wafer to crack in the peeling layer, wherein a portion of the first wafer remaining on the surface of the oxide layer is a top silicon layer, and the oxide layer is an insulating buried layer; and annealing the bonded wafer.

Abstract: The present disclosure provides a method for cleaning a bonding interface before bonding. The method includes: providing a first surface and a second surface for bonding, the first surface being a non-crystal surface and the second surface being a crystal surface; and cleaning the first surface and the second surface with ammonia respectively before bonding, wherein at least one of parameters of an ammonia concentration and a cleaning temperature for cleaning the first surface is higher than a counterpart of parameters for cleaning the second surface.

Abstract: The present disclosure provides a bonding method for a semiconductor substrate, which may improve flatness of a bonded substrate. The present disclosure further provides a bonded semiconductor substrate. The semiconductor substrate is thermally treated prior to bonding, and oxygen precipitates in the semiconductor substrate are partially or totally converted to interstitial oxygen atoms in the thermal treatment.

Abstract: The present disclosure provides an annealing method for improving interface bonding strength of a wafer. The method includes: providing a substrate, the substrate having a bonding interface; performing a first annealing step, wherein the first annealing step is practiced in an oxygen-containing atmosphere, and an oxidation protection layer is formed on a surface of the substrate through the annealing step; and performing a second annealing step upon the first annealing step, wherein a temperature of the second annealing step is higher than that of the first annealing step, and the second annealing step is practiced in a nitrogen-free environment.

Abstract: A gallium nitride high electron mobility transistor and a formation method therefor are provided. The transistor includes: a substrate; a gallium nitride channel layer disposed on the substrate; a first barrier layer disposed on the gallium nitride channel layer; a gate, a source and a drain disposed on the first barrier layer, the source and the drain being respectively disposed on two sides of the gate; and a second barrier layer disposed on a surface of the first barrier layer between the gate and the drain, a side wall of the second barrier layer being connected to a side wall on one side of the gate and being configured to generate two-dimensional hole gas. The high electron mobility transistor has a higher breakdown voltage.

Abstract: A method for preparing a substrate with an insulating buried layer includes: providing a substrate, the substrate having a supporting layer and an insulating layer arranged on a surface of the supporting layer; performing first ion implantation, implanting modified ions into the substrate, wherein a distance from an interface between the insulating layer and the supporting layer to a Gaussian distribution peak of modified ion concentration is less than 50 nm, such that the modified ions form a nano cluster in the insulating layer; and performing a second ion implantation, continuing to implant the modified ions into the insulating layer, wherein the ions are implanted in the same way as the first ion implantation, and a distance from a Gaussian distribution peak of modified ion concentration in this step to the Gaussian distribution peak of modified ion concentration in the first ion implantation is less than 80 nm.

Abstract: The present disclosure provides a method for preparing a substrate with a carrier trapping center. The method includes: implanting bubbling ions into the semiconductor substrate to form a splitting layer, and implanting modified ions into the insulating layer to form a nano cluster; providing a supporting substrate; bonding the supporting substrate to the semiconductor substrate by using the insulating layer as an intermediate layer; performing a first heat treatment for the bonded substrate such that a splitting layer is formed at the position where the bubbling ions are implanted, and causing the semiconductor substrate to split at the position of the splitting layer; performing rapid thermal annealing for the substrate; and performing a second heat treatment for the rapidly thermally annealed semiconductor substrate to consolidate the bonding interface and form the nano cluster at the position where the modified ions are implanted.

Abstract: A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.

Abstract: A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.

Abstract: A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.