Abstract: Provided is the following: a resin substrate layer; a thin-film transistor layer provided on the resin substrate layer, and having a stack of, in sequence, a gate insulating film, an interlayer insulating film, and a flattening film; and a light-emitting element layer provided on the thin-film transistor layer, with a plurality of first electrodes, a common edge cover that is common, a plurality of light-emitting function layers, and a second electrode that is common being stacked sequentially in correspondence with a plurality of subpixels constituting a display region. A non-display region that is in the form of an island within the display region has a through-hole. The non-display region includes a first light-blocking film provided on the periphery of the flattening film so as to cover the side wall of the periphery.

Abstract: An organic EL display device has a picture-frame region provided with: dam walls extending along an outer periphery of a display region to block an organic sealing layer; and a second lead wire running from toward the display region, crossing the dam walls, and extending out of the picture-frame region. The picture-frame region includes a spacer wall extending along the dam wall and provided to an outer periphery of a portion, of the dam wall, intersecting at least with the second lead wire. The spacer wall has an upper portion provided with a plurality of protruding portions at intervals along the spacer wall. The second lead wire extends to cross a portion of, the spacer wall, away from the protruding portions.

Abstract: A liquid crystal display device includes: a first substrate; a second substrate; a liquid crystal layer; a polarizer; and a phase difference layer, the liquid crystal display device further including a plurality of pixels arranged in a matrix, wherein each of the plurality of pixels includes a reflection region, the first substrate includes: a plurality of gate lines; a plurality of source lines; a plurality of thin film transistors; a plurality of pixel electrodes; and a reflective layer, the first substrate further includes: a plurality of touch sensor electrodes; and a plurality of touch lines each electrically connected to a corresponding one of the plurality of touch sensor electrodes, the reflective layer is divided into a plurality of reflective segments that are electrically independent from each other, and each of the plurality of reflective segments overlaps two or more of the plurality of pixel electrodes in a plan view.

Abstract: Provided is a liquid crystal display device with sufficiently reduced or prevented alignment defect generation and useful as an in-cell touch panel capable of providing display in the reflective mode. The liquid crystal display device includes first and second substrates and a liquid crystal layer. The first substrate includes a reflective layer reflecting light, first and second electrodes capable of generating a transverse electric field in the liquid crystal layer, and a first horizontal alignment film. At least one of the first electrode or the second electrode includes strip portions and a slit between adjacent two strip portions among the strip portions. The second substrate includes a second horizontal alignment film in contact with the liquid crystal layer. The liquid crystal layer includes liquid crystal molecules having a positive anisotropy of dielectric constant and is in a twist alignment during no voltage application.

Abstract: A second test portion includes a second test first terminal, a second test second terminal, a second test third terminal, and a second test fourth terminal electrically connected to a second test semiconductor layer via respective contact holes formed in a layered film of a gate insulating film and an interlayer insulating film, and the layered film of the gate insulating film and the interlayer insulating film in the second test portion is provided with an opening open upward between at least one of the second test first terminal, the second test second terminal, the second test third terminal, and the second test fourth terminal.

Abstract: A display substrate includes: a first wiring line located in a display region where an image is displayed; a second wiring line located in a non-display region where the image is not displayed; a first circuit unit located in the non-display region and including a first output section connected to the first wiring line and a first input section connected to the second wiring line; and a second circuit unit located in the non-display region and connected to the second wiring line but not connected to the first wiring line, wherein the second circuit unit is located adjacent to the first circuit unit along the second wiring line in the non-display region.

Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs each including an oxide semiconductor layer, a lower gate electrode positioned on the substrate side of the oxide semiconductor layer, and an upper gate electrode positioned on the oxide semiconductor layer on a side opposite from the substrate, a plurality of source wiring lines extending in a column direction, a plurality of upper gate wiring lines extending in a row direction, and a plurality of lower gate wiring lines extending in the row direction. The plurality of lower gate wiring lines include a first gate wiring line, and the plurality of upper gate wiring lines include a second gate wiring line partially overlapping the first gate wiring line via the lower gate insulating layer and the upper gate insulating layer.

Abstract: A light-emitting element includes: an anode; a cathode; an EML therebetween; and an HIL in contact with the anode between the anode and the EML. The anode contains a metal oxide, the HIL contains PVP and PEDOT:PSS, and the HIL contains the PVP in an amount of from 0.16 parts by weight inclusive to 1.5 parts by weight exclusive per unit part by weight of the PSS.

Abstract: A phased array antenna with high yield and excellent transmission and reception performance is provided. The phased array antenna includes a printed circuit board 10 including a plurality of first terminals, a TFT substrate 50 including a plurality of second terminals and being arranged to face the printed circuit board 10, and a plurality of conductors 30 connecting the first terminals and the second terminals, respectively. The printed circuit board includes a plurality of transmission/reception electrodes 12, and beamforming ICs 20 receiving control signals from the TFT substrate via the first terminals and adjusting phases of signals transmitted and received by transmission/reception electrodes according to the control signals.

Abstract: An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.

Abstract: Provided are a liquid crystal panel capable of controlling the viewing angle with less increase in thickness and a video display device including the liquid crystal panel. The video display device includes: a display panel displaying an image; and a liquid crystal panel. The display panel includes at least a polarizer. The polarizer in the display panel is opposite to the liquid crystal panel on the display panel side of the liquid crystal panel. The liquid crystal panel includes, between a pair of transparent substrates, electrodes A arranged at intervals in plan view, a liquid crystal layer, and an electrode B opposite to the electrodes A with the liquid crystal layer interposed therebetween, and includes a voltage application unit which applies voltage between the electrodes A and the electrode B.

Abstract: A common electrode driver includes an operational amplifier, a resistor, one end of which is connected to an inverting input terminal of the operational amplifier and the other end of which is connected to an output terminal of the operational amplifier, and an adjustment circuit that is configured to be able to adjust an internal combined resistance value in accordance with an applied polarity inversion driving method. The combined resistance value obtained when a one-column inversion driving method is applied is caused to be smaller than the combined resistance value obtained when a two-column inversion driving method is applied.

Abstract: An active matrix substrate includes pixel regions each including a pixel electrode and an oxide semiconductor TFT including an oxide semiconductor layer. Each pixel electrode is electrically connected to one of adjacent two of source bus lines. The oxide semiconductor layer in the oxide semiconductor TFT of each pixel region overlaps the pixel electrode of a first adjacent pixel region. The pixel electrode of the each pixel region partially overlaps the oxide semiconductor layer in a second adjacent pixel region. The source bus lines include first and second source bus lines adjacent to each other. Pixels sets each including two pixel regions whose pixel electrodes are connected to the first source bus line and pixel sets each including two pixel regions whose pixel electrodes are connected to the second source bus line are arranged alternately between the first and second source bus lines.

Abstract: The display device of the present invention includes, in the following order toward a viewer: a display panel; a semi-transparent mirror; a Pancharatnam-Berry lens configured to cause one-handed circularly polarized light incident thereon that is left-handed circularly polarized light or right-handed circularly polarized light to converge while causing opposite-handed circularly polarized light incident thereon to diverge; and a circularly polarized light-selective reflector.

Abstract: A driving circuit includes a first transistor outputting a drive signal, and a third transistor supplied with a reset signal. A source electrode of the first transistor is supplied with a first clock signal. A source electrode of the third transistor is supplied with a second clock signal. The second clock signal has a phase different from a phase of the first clock signal. The second clock signal has a voltage that remains at a high level for a time period from a start point to an end point within a time period throughout which a potential of a node is higher than a gate-on voltage of the third transistor. The start point is prior to a time point of supplying the reset signal. The end point falls between the time point of supplying the reset signal and a time point of stopping supplying the reset signal.

Abstract: A plurality of inversely tapered protruding portions are provided so as to surround a through-hole in a non-display region, each of the plurality of inversely tapered protruding portions includes a resin portion constituted by a resin substrate layer and separated by a plurality of substrate slits, and inorganic insulating layers provided on the resin portion, a first inorganic encapsulation film covers the plurality of inversely tapered protruding portions and the plurality of substrate slits, and a metal layer is provided on the inorganic insulating layer in at least one of the plurality of inversely tapered protruding portions.

Abstract: A detector includes a first electrode, a second electrode facing the first electrode with a space and forming a flow path for charged particles as objects to be detected between the first electrode and the second electrode, a third electrode arranged side by side with the second electrode on a downstream side in the flow path with respect to the second electrode and configured to collect the charged particles, and a potential supply circuit configured to supply a potential to at least one of the first electrode and the second electrode, in which the potential supply circuit includes a first inductor including a first input portion and a first output portion, and a second inductor including a second input portion and a second output portion, the first input portion of the first inductor is connected to a DC power supply, and the second input portion of the second inductor is connected to the first electrode or the second electrode.

Abstract: The relative positions of a first low-reflection layer and a second low-reflection layer are variable in a bendable portion. A main low-reflection structure has, on a surface facing a secondary low-reflection structure, an asperity pattern and a moth-eye structure. The asperity pattern has a sine-wave shaped surface in a sectional view. A single period of a sine wave constituting the sine-wave shaped surface is equal to an integral multiple of the width of a single pixel of a display device in a direction where the asperity pattern is arranged.

Abstract: A lighting device includes a plurality of light sources disposed side by side in a row direction and a column direction in one plane, a substrate on which the plurality of light sources are mounted, and a reflection member disposed covering the mounting surface of the substrate. The reflection member includes a plurality of insertion holes through which the light sources are respectively inserted, and a plurality of wall portions surrounding corresponding insertion holes of the plurality of insertion holes. A plane of the reflection member is partitioned into a plurality of reflective regions by the plurality of wall portions. The plurality of light sources are respectively disposed inside the reflective regions. An outer reflective region located at an outer periphery among the plurality of reflective regions has an area smaller than the area of an inner reflective region located on the inner side of the outer reflective region.

Abstract: A display device includes: a display panel including a HIGH power supply line and a LOW power supply line; and a scan signal line drive circuit including a unit circuit, wherein the unit circuit includes: a SET terminal; a RESET terminal; an output terminal; a first thin film transistor; a second thin film transistor including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, the second gate electrode being electrically connected to the SET terminal, one of the second source electrode and the second drain electrode being electrically connected to an internal node; and a third thin film transistor, the second gate electrode is an upper gate electrode, another one of the second source electrode and the second drain electrode is electrically connected to the HIGH power supply line, and the second thin film transistor further includes a lower gate electrode.