Abstract: A semiconductor memory device includes: a plurality of bit lines disposed on a substrate; a plurality of word lines and a plurality of data lines disposed on the substrate in a direction crossing with the bit lines; a plurality of memory cells disposed in a matrix at portions corresponding to respective crossing points of the bit lines and the word lines, each of the plurality of memory cells having at least one switching transistor and at least one ferroelectric capacitor including a ferroelectric film as an insulating film to form a non-volatile ferroelectric memory storing information by a polarization direction of the ferroelectric film; a substrate voltage generating circuit which supplies a negative substrate voltage to the substrate; and a power-on reset circuit which output and applies a predetermined positive voltage to the word lines during a time period from a power-on until the substrate voltage is stabilized.