Abstract: In accordance with the levels of input signals, a recall signal or store signal is generated and held. Based on the signal currently held, only one of the read/write timing circuit, recall timing circuit and store timing circuit is enabled for operation with the operation of the other two timing circuit disabled: the recall timing circuit is enabled when the recall signal is held, the store timing circuit when the store signal is held, and the read/write timing circuit when neither the recall signal nor the store signal is held. Therefore, once one operation mode has been selected by setting the input signals to a prescribed combination of levels, the selected mode is held until another operation mode is selected. Since there is no need to input the nonvolatile enable signal NE signal during the recall operation, the external input timing can be simplified.

Abstract: A display elect:rode substrate comprising at least two, first and second, TFTs connected in series to each picture element, wherein the first and second thin film transistors are Juxtaposed on the same one of the gate bus lines, part of the gate bus line functions as gate electrodes of the first and second thin film transistors, a source electrode of the first thin film transistor is connected to the source bus line, a drain electrode of the first thin film transistor is connected to a source electrode of the second thin film transistor, and a drain electrode of the second thin film transistor is connected to the picture element electrode, whereby a picture element defect caused by a short-circuit defect of the TFTs can be reduced.