Patents Assigned to Shellcase Ltd.
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Patent number: 6972480Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: GrantFiled: June 16, 2003Date of Patent: December 6, 2005Assignee: Shellcase Ltd.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Publication number: 20050104179Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.Type: ApplicationFiled: July 2, 2004Publication date: May 19, 2005Applicant: SHELLCASE LTD.Inventors: Gil Zilber, Julia Aksenton, Vage Oganesian
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Publication number: 20040251525Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: SHELLCASE LTD.Inventors: Gil Zilber, Reuven Katraro, Julia Aksenton, Vage Oganesian
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Patent number: 6777767Abstract: A crystalline substrate based device includes a crystalline substrate having formed thereon a microstructure, and a transparent packaging layer which is sealed over the microstructure by an adhesive and defines therewith at least one gap between the crystalline substrate and the packaging layer. The microstructure receives light via the transparent packaging layer.Type: GrantFiled: November 29, 2000Date of Patent: August 17, 2004Assignee: Shellcase Ltd.Inventor: Avner Pierre Badehi
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Publication number: 20040076797Abstract: A crystalline substrate based device including a crystalline substrate having formed thereon a microstructure and at least one packaging layer which is formed over the microstructure and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer and at least one opening in the packaging layer communicating with the at least one gap.Type: ApplicationFiled: October 22, 2002Publication date: April 22, 2004Applicant: SHELLCASE LTD.Inventors: Gil Zilber, Reuven Katraro, Doron Teomim
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Patent number: 6646289Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.Type: GrantFiled: September 22, 2000Date of Patent: November 11, 2003Assignee: Shellcase Ltd.Inventor: Avner Badehi
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Patent number: 6624505Abstract: This invention discloses a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface. A method for producing packaged integrated circuits is also disclosed.Type: GrantFiled: January 11, 2001Date of Patent: September 23, 2003Assignee: Shellcase, Ltd.Inventor: Avner Badehi
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Publication number: 20030151124Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.Type: ApplicationFiled: March 11, 2003Publication date: August 14, 2003Applicant: SHELLCASE, LTD.Inventor: Avner Badehi
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Publication number: 20010018236Abstract: This invention discloses a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure; and at least one packaging layer which is sealed over the microstructure by means of an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer.Type: ApplicationFiled: November 29, 2000Publication date: August 30, 2001Applicant: Shellcase Ltd.Inventor: Avner Pierre Badehi
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Patent number: 6117707Abstract: A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer, each of the integrated circuits including a multiplicity of pads and thereafter slicing the wafer, thereby to define a plurality of integrated circuit elements, and wherein the step of slicing exposes sectional surfaces of the multiplicity of pads. Apparatus for carrying out the method and integrated circuit devices are also described and claimed.Type: GrantFiled: July 29, 1996Date of Patent: September 12, 2000Assignee: Shellcase Ltd.Inventor: Peirre Badehi
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Patent number: 6040235Abstract: A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer having first and second planar surfaces, each of the integrated circuits including a multiplicity of pads, waferwise attaching to both said surfaces of the wafer a layer of protective material, thereafter partially cutting into the wafer and the protective material attached thereto, thereby to define notches along outlines of a plurality of prepackaged integrated circuit devices, forming metal contacts onto the plurality of prepackaged integrated circuit devices while they are still joined together on the wafer, at least a portion of said metal contacts extending into the notches and thereafter separating the plurality of prepackaged integrated circuit devices into individual devices. Integrated circuits produced according to the method are also disclosed and claimed.Type: GrantFiled: August 19, 1996Date of Patent: March 21, 2000Assignee: Shellcase Ltd.Inventor: Pierre Badehi
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Patent number: 6022758Abstract: A process of forming a packaged integrated circuit by aperturing a discrete packaging layer attached on a silicon substrate. A plurality of solder leads are formed on the layer. Electrical connections are formed from the leads to pads on the substrate.Type: GrantFiled: February 21, 1997Date of Patent: February 8, 2000Assignee: Shellcase Ltd.Inventor: Pierre Badehi
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Patent number: 5980663Abstract: This invention discloses a method of bonding a lower substrate with an upper substrate comprising applying an adhesive (56) on at least one of the lower (12) and the upper (14) substrates, and rotating the lower and the upper substrates thereby to create a centrifugal force which causes the adhesive to spread between the lower and the upper substrates with a substantially uniform thickness, while applying a pressure upon the upper substrate thereby to bond the lower and upper substrates. The invention also discloses an apparatus for bonding the lower substrate with the upper substrate.Type: GrantFiled: February 27, 1998Date of Patent: November 9, 1999Assignee: Shellcase Ltd.Inventor: Pierre Badehi
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Patent number: 5716759Abstract: A method for three dimensional lithography including the steps of providing a substrate (44) having surfaces extending in three dimensions and a light sensitive coating and illuminating the substrate via a mask (40) with light impinging on the surfaces at a non-perpendicular angle with respect thereto.Type: GrantFiled: June 17, 1996Date of Patent: February 10, 1998Assignee: Shellcase Ltd.Inventor: Pierre Badehi