Abstract: A timing control chip includes a pulse signal generation module for generating first and second pulse signals, a data signal sending module having a data signal including valid and invalid data segments, and a synthesis module for synthesizing the first and second pulse signals into the invalid data segment to form a synthesized data signal and then transfer it to the data signal sending module. The data signal sending module is to connect a data driver chip to make the data driver chip decompose the synthesized data signal into the first and the second pulse signal, grab a state of the second pulse signal when the first pulse signal is at a first edge and control a polarity of an outputted driving voltage according to the grabbed state of the second pulse signal. The invention further provides a data driver chip and a driving circuit.