Patents Assigned to SHENZHEN CHIPULLER CHIP TECHNOLOGY CO., LTD
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Patent number: 11947972Abstract: Described is an apparatus comprising a semiconductor interconnect substrate and an interface. The semiconductor interconnect substrate may be electrically coupled to one or more components mounted thereon. The interface may be operable to carry a configuration command set to the one or more components in a normal operation mode subsequent to a power-up mode.Type: GrantFiled: August 5, 2021Date of Patent: April 2, 2024Assignee: Shenzhen Chipuller Chip Technology Co., LTDInventors: Meng Yan, Omar Mahmoud Afdal Alnaggar, Myron O. Shak, Soheil Gharahi, William Kelsey
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Patent number: 11728909Abstract: Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.Type: GrantFiled: April 12, 2022Date of Patent: August 15, 2023Assignee: Shenzhen Chipuller Chip Technology Co., LTDInventors: Jawad Nasrullah, Omar Alnaggar, Hanfeng Wang, Mohamed Sameh Mahmoud
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Patent number: 11720729Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.Type: GrantFiled: May 25, 2022Date of Patent: August 8, 2023Assignee: Shenzhen Chipuller Chip Technology Co., LTD.Inventors: Danielle Morton, Rick Yan
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Publication number: 20230124949Abstract: Described herein are mechanisms and methods for blocking the propagation of signals to Integrated Circuit (IC) components that have been power gated, rather than simply suffering from leakage through signals that might not be parked in a low state. In some embodiments, switches that block the flow of current in such signals may enable turning off power to any IC component and not just to circuits on an IC component that make sole use of protocols that are friendly to power gating. This may advantageously increase power savings, by permitting more portions of a system in an idle state to be power gated, or by reducing or eliminating leakage in signals on boundaries of blocks being power gated, or both.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Applicant: Shenzhen Chipuller Chip Technology Co., LTD.Inventor: Mathew Salazar
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Patent number: 11573623Abstract: Described herein are mechanisms and methods for blocking the propagation of signals to Integrated Circuit (IC) components that have been power gated, rather than simply suffering from leakage through signals that might not be parked in a low state. In some embodiments, switches that block the flow of current in such signals may enable turning off power to any IC component and not just to circuits on an IC component that make sole use of protocols that are friendly to power gating. This may advantageously increase power savings, by permitting more portions of a system in an idle state to be power gated, or by reducing or eliminating leakage in signals on boundaries of blocks being power gated, or both.Type: GrantFiled: February 3, 2021Date of Patent: February 7, 2023Assignee: Shenzhen Chipuller Chip Technology Co., LTDInventor: Mathew Salazar
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Patent number: 11476182Abstract: Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.Type: GrantFiled: October 8, 2018Date of Patent: October 18, 2022Assignee: Shenzhen Chipuller Chip Technology Co., LTDInventors: Zhiquan Luo, Jawad Nasrullah, Omar Mahmoud Afdal Alnaggar
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Publication number: 20220329245Abstract: Described are concepts related to the field of programmable interconnect substrates used in packaging electronics, and to stacked integrated circuits produced for application in low power and small form factor designs with fast prototyping and short mass-production cycle times. The concepts facilitate the dynamic reconfiguration of routing resources in the presence of an active system, and the tuning of routing paths to meet power and performance metrics.Type: ApplicationFiled: June 28, 2022Publication date: October 13, 2022Applicant: Shenzhen Chipuller Chip Technology Co., LTD.Inventors: Meng Yan, Omar Mahmoud Adfal Alnagger, Myron O. Shak, Soheil Gharahi
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Publication number: 20220319967Abstract: Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.Type: ApplicationFiled: June 21, 2022Publication date: October 6, 2022Applicant: Shenzhen Chipuller Chip Technology Co., LTD.Inventors: Zhiquan Luo, Jawad Nasrullah, Omar Mahmoud Afdal Alnaggar
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Publication number: 20220292242Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.Type: ApplicationFiled: May 25, 2022Publication date: September 15, 2022Applicant: Shenzhen Chipuller Chip Technology Co., LTD.Inventors: Danielle Morton, Rick Yan
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Patent number: 11418196Abstract: Described are concepts related to the field of programmable interconnect substrates used in packaging electronics, and to stacked integrated circuits produced for application in low power and small form factor designs with fast prototyping and short mass-production cycle times. The concepts facilitate the dynamic reconfiguration of routing resources in the presence of an active system, and the tuning of routing paths to meet power and performance metrics.Type: GrantFiled: June 28, 2018Date of Patent: August 16, 2022Assignee: Shenzhen Chipuller Chip Technology Co., LTDInventors: Meng Yan, Omar Mahmoud Adfal Alnagger, Myron O. Shak, Soheil Gharahi
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Publication number: 20220253584Abstract: Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.Type: ApplicationFiled: April 25, 2022Publication date: August 11, 2022Applicant: Shenzhen Chipuller Chip Technology Co., LTD.Inventors: Hao Hua, Jawad Nasrullah
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Publication number: 20220239389Abstract: Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.Type: ApplicationFiled: April 12, 2022Publication date: July 28, 2022Applicant: Shenzhen Chipuller Chip Technology Co., LTD.Inventors: Jawad Nasrullah, Omar Alnaggar, Hanfeng Wang, Mohamed Sameh Mahmoud
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Patent number: 11379642Abstract: Described is a method comprising a processing, an establishing, and/or a determining. In the processing, an inputted capabilities list including one or more hardware design capabilities may be processed. In the establishing, one or more candidate components for the one or more hardware design capabilities may be established. In the determining, a set of unique candidate netlists capable of satisfying the one or more hardware design capabilities may be determined, the set of unique candidate netlists being based upon the set of candidate components.Type: GrantFiled: October 2, 2020Date of Patent: July 5, 2022Assignee: Shenzhen Chipuller Chip Technology Co., LTDInventors: Danielle Morton, Rick Yan
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Patent number: 11361138Abstract: Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.Type: GrantFiled: August 9, 2017Date of Patent: June 14, 2022Assignee: Shenzhen Chipuller Chip Technology Co., Ltd.Inventors: Hao Hua, Jawad Nasrullah
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Patent number: 11329734Abstract: Described are methods and apparatuses pertaining to stacked integrated circuits having application in ultra-low-power and small form factor design, with fast prototyping and mass-production cycle time, including application for millimeter wave radio frequency circuits.Type: GrantFiled: October 16, 2020Date of Patent: May 10, 2022Assignee: SHENZHEN CHIPULLER CHIP TECHNOLOGY CO., LTDInventors: Jawad Nasrullah, Omar Alnaggar, Hanfeng Wang, Mohamed Sameh Mahmoud