Abstract: A receiver circuit is disclosed. The receiver circuit includes one or more receiver antennas configured to receive a plurality of RF signals transmitted from a transmitter circuit including one or more transmit antennas, an RF chain configured to generate a plurality of digitized samples of the received RF signals, and a controller configured to receive the digitized samples, to calculate a plurality of additional samples, and to calculate a measured angle of arrival or angle of departure (AoA or AoD) of the RF signals based on the digitized samples and the calculated additional samples.

Abstract: A signal driving method is provided. One signal driving cycle includes two signal driving periods in which drive signals are applied to P detection electrodes. The method comprises, in a first period, applying non-inverting and inverting drive signals respectively to M adjacent detection electrodes and N adjacent detection electrodes. The non-inverting and inverting drive signals respectively applied to the M and N electrodes cancel each other out, M+N?P and |M?N|?Q. The method further comprises, in a second period, applying the non-inverting and inverting drive signals respectively to K adjacent detection electrodes and L adjacent detection electrodes. The non-inverting and inverting drive signals respectively applied to the K and L electrodes cancel each other out, K+L?P, |K?L|?Q and M+K?P.

Abstract: Embodiments of the present disclosure disclose a method for detecting ambient light sensing value, an electronic device and a storage medium. The method includes: collecting a light sensing value when a display screen is in an on state, to obtain a first light sensing value; collecting a light sensing value when the display screen is in an off state, to obtain a second light sensing value; calculating a difference between the first light sensing value and the second light sensing value, to obtain a light sensing value drop depth; acquiring a first calibration coefficient or a second calibration coefficient; calculating the ambient light sensing value based on the first light sensing value, the light sensing value drop depth and the first calibration coefficient; or calculating the ambient light sensing value based on the second light sensing value, the light sensing value drop depth and the second calibration coefficient.

Abstract: Embodiments of the present application disclose a fingerprint identification apparatus and an electronic device, which can simplify an optical path laminated structure and processing process, thereby improving efficiency of mass production. The fingerprint identification apparatus includes: a fingerprint sensor chip; an infrared radiation cut filter layer provided above the fingerprint sensor chip; a light blocking layer provided on an upper surface of the infrared radiation cut filter layer by means of coating film, the light blocking layer being provided with a first hole array, and cross sections of holes in the first hole array being inverse trapezoid; a light transmitting dielectric layer including first color filter units, the first color filter units being formed in part of the holes in the first hole array to cover the part of the holes; and a microlens array provided above the light transmitting dielectric layer.

Abstract: A capacitor includes: a substrate; a first trench entering the substrate downward from the upper surface of the substrate; a laminated structure provided in the first trench and including m dielectric layers and n conductive layers, the m dielectric layers and the n conductive layers forming a structure that a conductive layer and a dielectric layer are adjacent to each other, each dielectric layer of the m dielectric layers including at least one high-k insulating material with a relative dielectric constant k greater than a first threshold value, and each conductive layer of the n conductive layers including at least one high work function conductive material with a work function greater than a second threshold value, where m and n are positive integers; and a first electrode electrically connected to all odd-numbered conductive layers, and a second electrode electrically connected to all even-numbered conductive layers.

Abstract: A method and an apparatus for pressure detection, an active pen, a touch control chip and an electrode device are provided, configured to detect a pressure of the active pen on a screen. The active pen includes a pressure sensor, a wireless communication module and a tip electrode, and the pressure sensor is configured to detect the pressure generated by the active pen. The method includes: determining a second pressure level corresponding to the pressure, according to a detection signal corresponding to a first driving signal output by the tip electrode, when a pressure signal of a first pressure level corresponding to the pressure sent by the wireless communication module is not received; and displaying handwriting of the active pen, by the screen, according to the second pressure level. The method can reduce time delay of a response of a first writing of the active pen.

Abstract: An active capacitive pen is disclosed, including: a barrel; a first electrode disposed at an end of the barrel, an end of the first electrode away from the barrel serving as a tip of the active capacitive pen; a second electrode disposed on the barrel and spaced apart from the first electrode in an axial direction of the barrel; a third electrode disposed on the barrel and located between the first electrode and the second electrode in the axial direction of the barrel; a switching circuit, connected with the second electrode and the third electrode and configured to electrically connect the third electrode with the first electrode, or disconnect the third electrode from the second electrode. Also disclosed is an electronic terminal with the active capacitive pen.

Abstract: A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit comprises: a latch and a signal output module, wherein a first input of the latch is connected to a power supply voltage, a first output of the latch is connected to a ground voltage, a second input of the latch is connected to a third output of the latch, a third input of the latch is connected to a second output of the latch, and the second output or the third output is connected to the signal output module. The power glitch signal detection circuit could detect a power glitch on the power supply voltage or the ground voltage, and the power glitch signal detection circuit has the advantages of low power consumption, small area, high speed, high sensitivity and strong portability.

Abstract: A method for optimizing power consumption for Narrowband Internet of Things devices, UEs, in idle mode using a coverage class specific paging configuration, where carriers for paging are partitioned by coverage class, whereas the coverage class specific paging configuration, broadcasted by a system information exchanged between the base station and the UE, is extended by an additional NRSRP rsrp-ThresholdPcch threshold, whereas the UE selects one carrier for paging with a Narrowband Reference signal received power (NRSRP) smaller than the rsrp-ThresholdPcch threshold or if a UE is not reachable the eNodeB expands a paging area for the considered UE stepwise into other paging coverage classes in order to reach the UE.

Abstract: A capacitance detection circuit is provided, which includes a capacitance control module, a charge conversion module and a filter module connected with each other. The capacitance control module controls a capacitor to be charged/discharged for multiple times and generates a digital voltage signal according to an amount of received charges. The capacitor releases all stored charges after being charged to a preset voltage during each charge/discharge. In response to the digital voltage signal being at a high level, the charge conversion module outputs negative charges with a preset charge amount to the capacitance control module. The preset charge amount is greater than or equal to an amount of the stored charges when the capacitor is charged to the preset voltage. The filter module obtains a value representing a capacitance of the capacitor according to the digital voltage signal.

Abstract: A hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device is described, such as for incorporation into in-pixel circuitry of an imaging pixel array to provide both reset and dual conversion gain features. The Fe-MOSFET includes source and drain regions implanted in a semiconductor substrate and separated by a channel region. The source region can be the floating diffusion region of a photosensor. A gate structure is deposited on the substrate directly above at least the channel region and an isolating layer is formed on the surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolating layer is split into a Fe segment of ferroelectric material that can be written to different polarization states for conversion gain control, and a dielectric segment that can be used for current channel formation in the channel region.

Abstract: The present disclosure discloses a driving circuit and a related chip and electronic device. The driving circuit is configured to drive a load and includes: a control unit, configured to generate a first control signal and a second control signal; a first output terminal, coupled to the capacitive touch screen; a mutual capacitive driving circuit, including: a first pull-up unit, configured to selectively pull up the first output terminal coupled to a high voltage level according to the first control signal; a first pull-down unit, configured to selectively couple the first output terminal to a low voltage level according to the second control signal; a first low-pass filter circuit, coupled between the control unit and the first pull-up unit; and a second low-pass filter circuit, coupled between the control unit and the first pull-down unit.

Abstract: Techniques are described for passive three-dimensional (3D) image sensing based on chromatic differentiation. For example, an object can be imaged by using a photodetector array to detect light reflected off of the object and focused through a lens onto the array. Light components of different wavelengths tends to be focused through the lens to different focal lengths, which can tend to impact the brightness of each wavelength as detected. For example, if the detector array is closer to a shorter-wavelength focal plane, a white spot will tend to be detected with a higher magnitude of blue light components than of red light components. Ratios of brightness magnitudes for different wavelengths vary in a manner that strongly correlates to object distance from the lens. Embodiments exploit this correlation to passively detect object distance. Some embodiments further provide various types of distance and/or chromatic calibration to further facilitate such detection.

Abstract: Provided are an apparatus for acquiring a depth image, a method for fusing depth images, and a terminal device. The apparatus for acquiring a depth image includes an emitting module, a receiving module, and a processing unit. The emitting module is configured to emit a speckle array to an object, where the speckle array includes p mutually spaced apart speckles. The receiving module includes an image sensor. The processing unit is configured to receive the pixel signal and generate a sparse depth image based on the pixel signal, align an RGB image at a resolution of a*b with the sparse depth image, and fuse the aligned sparse depth image with the RGB image using a pre-trained image fusion model to obtain a dense depth image at a resolution of a*b.

Abstract: An image sensor includes ADCs, each including a comparator receiving a ramp signal and an image signal, and generating a comparator output. Each ADC also includes a counter ceasing to change a digital count value in response to a change in the comparator output. The digital count value has a first resolution. Each ADC also includes a delay line circuit including a delay line generating a first digital value encoding a duration of a period of the counter clock and generating a second digital value encoding a first portion of the period of the counter clock. Each ADC also includes a delay to digital circuit generating a digital output value based on the first and digital values. The digital output value encodes a second value of the ramp signal, where the digital count value has a second resolution that is greater than the first resolution.

Abstract: Embodiments of the present application disclose a fingerprint identification apparatus and an electronic device. The fingerprint identification apparatus is used to be disposed under a display screen and includes a first filter layer and a fingerprint sensor, and the first filter layer is disposed above the fingerprint sensor, the first filter layer includes a plurality of first filter units, and the plurality of first filter units are disposed in a region of the first filter layer corresponding to an edge region of the fingerprint sensor; sensing units of the edge region of the fingerprint sensor are configured to receive a light signal returned by a finger above the display screen and filtered by the plurality of first filter units; and sensing units of a middle region of the fingerprint sensor are configured to receive a light signal returned by the finger, to generate a fingerprint image of the finger.

Abstract: The present application discloses an amplifier circuit, a chip and an electronic device, which generates a positive output signal and a negative output signal according to a positive input signal and a negative input signal, wherein the positive input signal and the negative input signal have a corresponding input differential-mode voltage and input common-mode voltage, and the positive output signal and the negative output signal have a corresponding output differential-mode voltage and output common-mode voltage, and the amplifier circuit includes: an amplifying unit, configured to receive the positive input signal and the negative input signal and generate the positive output signal and the negative output signal; and an attenuation unit, including: a positive common-mode capacitor and a negative common-mode capacitor, configured to attenuate the input common-mode voltage below a first specific frequency.

Abstract: Some embodiments of the present disclosure provide a signal processing system, a chip and an active stylus. The signal processing system includes: a pre-amplifier circuit, configured to pre-amplify a received DSSS signal and output a pre-amplified DSSS signal; a low-pass filter circuit, configured to filter the pre-amplified DSSS signal and output a filtered DSSS signal; an analog-to-digital converter circuit, configured to sample the filtered DSSS signal and output a sampled DSSS signal; a noise detecting and filtering-out circuit, configured to filter out a noise in the sampled DSSS signal and output a noise-filtered DSSS signal; and a digital demodulation circuit, configured to demodulate the noise-filtered DSSS signal to output a demodulated signal. The signal processing system can have strong anti-interference ability and high sensitivity through the noise detecting and filtering-out circuit and automatically controlling a gain of the pre-amplifier circuit.

Abstract: A DLL circuit that has a programmable output frequency is provided. The DLL circuit uses a single delay line to produce the multiple frequencies. In various embodiments, the delay line is configured to receive an input clock defining an input clock period. The delay line comprises delay stages, each configured to generate a corresponding output clock having a phase relative to the input clock based on a delay of the delay line. In those embodiments, a control circuit is configured to change the delay of the delay line so as to cause a phase difference between the input clock and a sensed output clock to be substantially equal to the input clock period. An edge combiner is configured to generate a DLL output clock based on the output clocks of the delay stages and presents an equal schematic load for each of the output clocks of the delay stages.

Abstract: The present disclosure provides a secure booting method, apparatus, device for an embedded program and a storage medium. The method includes: when a boot program is running, acquiring data of an application program, including signature information, public key information, parameter information, encrypted data, and a digital check code; performing signature check according to the signature information; performing integrity check according to the digital check code if the signature check passes; and performing data decryption according to the public key information and the parameter information if the integrity check passes. The present disclosure may improve information security.