Abstract: The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

Abstract: Embodiments of this application provide a power supply voltage control method and apparatus, a blockchain server, and a storage medium. The method includes: determining a voltage determination parameter based on a ratio of a first value to a second value, where the first value is a number of cores in an operating state in a blockchain server, and the second value is a total number of cores in the blockchain server; determining a target voltage value of a power supply of the blockchain server based on the voltage determination parameter; and controlling a value of an output voltage of the power supply to be the target voltage value.

Abstract: A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (?2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

Abstract: The present disclosure relates to a method for providing clock frequencies for computing cores, a chip and a data processing device. The method includes: causing a main clock frequency unit to provide a first main clock frequency for computing cores; testing the computing cores operating at the first main clock frequency to determine whether a pass rate of the computing cores is greater than an upper threshold or less than a lower threshold; when the pass rate is less than the lower threshold, causing an auxiliary clock frequency unit to provide a lower first auxiliary clock frequency for computing cores abnormally operating, causing the main clock frequency unit to providing the first main clock frequency for the remaining computing cores; when the pass rate is greater than the upper threshold, causing the main clock frequency unit to provide a higher second main clock frequency for the computing cores.

Abstract: The present disclosure relates to a D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

Abstract: A single-phase immersion liquid cooling system, a liquid cooling method, and a storage medium are provided.

Abstract: The present disclosure relates to a training method for a parameter configuration model, a parameter configuration method, and a parameter configuration device.

Abstract: A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

Abstract: The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device.

Abstract: A method and an apparatus for generating a video digest, and a readable storage medium are provided. The method is applied to a video acquisition device that includes a hardware unit configured to obtain movement information in real time, the movement information includes speed information and direction information of the video acquisition device. The method includes: starting acquisition of a video signal in response to an acquisition start instruction, and recording movement information corresponding to each frame during the acquisition of the video signal; determining a frequency for key frame extraction according to the movement information corresponding to each frame; determining a key frame from the acquired video signal according to the frequency for key frame extraction; and in response to an acquisition end instruction, generating a video digest according to the key frame.

Abstract: The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device.

Abstract: The present disclosure relates to a phase-locked loop circuit and a signal processing device.

Abstract: Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

Abstract: The present disclosure relates to a training method for a parameter configuration model, a parameter configuration method, and a parameter configuration device.

Abstract: The present application discloses a liquid cooled electronic device. The liquid cooled electronic device comprises a chassis unit. The chassis unit is circumferentially closed relative to a first direction. A first accommodating space extending in the first direction is formed within the chassis unit. A liquid cooled computing unit and a liquid cooled power supply unit that are electrically connected are arranged in the first accommodating space. The liquid cooled computing unit and the liquid cooled power supply unit are respectively inserted into the first accommodating space through a first guide rail and a second guide rail. The first guide rail and the second guide rail are arranged in parallel in the first direction. That is, the liquid cooled computing unit and the liquid cooled power supply unit are arranged in parallel via the parallel arrangement of the first guide rail and the second guide rail.

Abstract: A method and apparatus for starting up a digital currency data processing device, and a digital currency data processing device. The digital currency data processing device includes a hash board including a plurality of hash chip groups. The method includes: transmitting a startup signal to a refrigerating part of a data processing device before turning on a power supply; turning on the power supply; and controlling respective hash chips in each hash chip group to gradually and synchronously turn on cores. The above arrangement improves voltage balance of a hash board, and also ensures the accuracy of a clock signal.

Abstract: A liquid-cooled plate radiator is disclosed. The liquid-cooled plate radiator includes a radiator body. A coolant liquid runner for circulating a coolant liquid is formed inside the radiator body. The coolant liquid runner includes a plurality of radiating sub-runners. Then, a plurality of fin units are arranged on the radiating sub-runners along a flow direction of the coolant liquid. The fin unit has a plurality of fins extending side by side along the flow direction of the coolant liquid. Moreover, the fins of the front and rear adjacent fin units on the radiating sub-runners are staggered, thereby increasing the radiating area, enhancing the disturbance of the coolant liquid when flowing inside the radiating sub-runners, and improving the radiating efficiency. Thus, the technical problems of limited radiating area and low radiating efficiency caused by a single linear coolant liquid runner are solved.

Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: The present disclosure relates to a composite logic gate circuit, including: a simple logic gate circuit including a first logic gate circuit and an inverter circuit, a first PMOS transistor, and a first NMOS transistor. The first logic gate circuit is configured to receive a first input signal and a second input signal, and to output a first output signal. The inverter circuit includes a second PMOS transistor and a second NMOS transistor. A source of the second PMOS transistor is coupled to a power input terminal, a drain is coupled to a drain of the second NMOS transistor, and a gate is configured to receive the first output signal. A source of the second NMOS transistor is coupled to a ground terminal, and a gate is configured to receive the first output signal. A source of the first PMOS transistor is coupled to the drain of the second PMOS transistor, a drain is coupled to a drain of the first NMOS transistor, and a gate is configured to receive a third input signal.

Abstract: The present disclosure relates to a processor and a computing system. A processor is provided, including: a pipeline stage, including sequential device(s); and a first clock driving circuit, configured to provide a clock signal to the pipeline stage, wherein the first clock driving circuit includes: a plurality of first clock paths, configured to provide corresponding clock signals respectively; a first selector, configured to select a clock signal from the clock signals provided by the plurality of first clock paths for the pipeline stage.