Abstract: Embodiments of this application provide a chip frequency control method and apparatus, a blockchain server, and a storage medium. The method includes: determining a real-time computing power ratio of a chip of a blockchain server, a real-time temperature of the chip, and a real-time voltage of the chip; and adjusting a setting frequency of the chip based on a first comparison result of the real-time computing power ratio with a reference computing power ratio of the chip, a second comparison result of the real-time temperature with a reference temperature of the chip, and a third comparison result of the real-time voltage with a reference voltage of the chip, wherein the reference computing power ratio, the reference temperature, and the reference voltage are determined when the blockchain server undergoes a frequency rising phase after start-up and enters a working status. When an exception occurs in the chip, timely and appropriate response can improve stability of the blockchain server.

Abstract: Disclosed is a method for determining configuration parameters of a data processing device, including: operating the data processing device by using configuration parameters, which are universal optimization configuration parameters obtained according to a universal operating parameter model; during the operating process, changing the configuration parameters to obtain a dedicated operating parameter data set, which includes a plurality of groups of operating parameters, each of which includes configuration parameters and capability parameters of the data processing device when the data processing device is operating under the configuration parameters; executing model training by using the dedicated operating parameter data set to obtain a dedicated operating parameter model; and obtaining optimal configuration parameters according to the dedicated operating parameter model, and operating the data processing device according to the optimal configuration parameters, where the optimal configuration parameters a

Abstract: The present disclosure relates to an apparatus and a method for a real-time clock (RTC) module of a system-on-chip (SoC), and provides an apparatus for powering battery-powered RTC module of an SoC. The apparatus is integrated in the RTC module and comprises: a first regulator stage comprising one or more regulators, wherein the first regulator stage is configured to provide a core power supply voltage (VDD_CORE) on the basis of battery output voltage (VDD_BAT); and a crystal oscillator I/O unit, the crystal oscillator I/O unit being powered by the core power supply voltage (VDD_CORE) and an I/O power supply voltage (VDD_IO), wherein the apparatus directly provides the battery output voltage (VDD_BAT) as the I/O power supply voltage (VDD_IO).

Abstract: This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.

Abstract: Disclosed in embodiments of the present application are a liquid-cooling heat dissipation apparatus, a liquid-cooling data processing device and a temperature equalization method. The liquid-cooling heat dissipation apparatus includes a housing unit and a first liquid-cooling plate arranged in the housing unit. A first electronic unit and a second electronic unit are arranged on a first cooling surface and a second cooling surface arranged oppositely of the first liquid-cooling plate respectively, and the first electronic unit and the second electronic unit may be, for example, hashboards, that is, in the liquid-cooling heat dissipation apparatus provided in the embodiment of the present application, one liquid-cooling plate is correspondingly provided with two hashboards.

Abstract: A data processing device and a data processing system are provided. The data processing device includes a housing, which is thermally conductive and defines a sealed accommodating cavity; a hashboard, which is arranged in the accommodating cavity and is in fixed connection to the housing; a control board, which is in communicative connection to the hashboard; and a power supply module, which is in electrical connection to the hashboard.

Abstract: A memory management method for a device, and a memory management device and a computing system.

Abstract: The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Abstract: Embodiments of this application provide a power supply voltage control method and apparatus, a blockchain server, and a storage medium. The method includes: determining a voltage determination parameter based on a ratio of a first value to a second value, where the first value is a number of cores in an operating state in a blockchain server, and the second value is a total number of cores in the blockchain server; determining a target voltage value of a power supply of the blockchain server based on the voltage determination parameter; and controlling a value of an output voltage of the power supply to be the target voltage value.

Abstract: The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

Abstract: A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (?2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

Abstract: The present disclosure relates to a method for providing clock frequencies for computing cores, a chip and a data processing device. The method includes: causing a main clock frequency unit to provide a first main clock frequency for computing cores; testing the computing cores operating at the first main clock frequency to determine whether a pass rate of the computing cores is greater than an upper threshold or less than a lower threshold; when the pass rate is less than the lower threshold, causing an auxiliary clock frequency unit to provide a lower first auxiliary clock frequency for computing cores abnormally operating, causing the main clock frequency unit to providing the first main clock frequency for the remaining computing cores; when the pass rate is greater than the upper threshold, causing the main clock frequency unit to provide a higher second main clock frequency for the computing cores.

Abstract: The present disclosure relates to a D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

Abstract: A single-phase immersion liquid cooling system, a liquid cooling method, and a storage medium are provided.

Abstract: The present disclosure relates to a training method for a parameter configuration model, a parameter configuration method, and a parameter configuration device.

Abstract: A computing device and a computing system for digital currency are disclosed. The computing system comprises: computing devices (comprising first and second computing devices) each comprising two ports; and a signal transmission path connecting the computing devices in series. Each computing device is connected to the signal transmission path via the two ports. The first computing device is configured to receive, from the signal transmission path through one of the two ports, a signal specific to an address of the first computing device to a local storage device thereof. The second computing device is configured to receive, from the signal transmission path through one of the two ports, a signal to a local storage device thereof, and forward the signal, which is not specific to an address of the second computing device, or an adjusted version of the signal to the signal transmission path through one of the ports.

Abstract: The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device.

Abstract: The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard, and a computing device.

Abstract: A method and an apparatus for generating a video digest, and a readable storage medium are provided. The method is applied to a video acquisition device that includes a hardware unit configured to obtain movement information in real time, the movement information includes speed information and direction information of the video acquisition device. The method includes: starting acquisition of a video signal in response to an acquisition start instruction, and recording movement information corresponding to each frame during the acquisition of the video signal; determining a frequency for key frame extraction according to the movement information corresponding to each frame; determining a key frame from the acquired video signal according to the frequency for key frame extraction; and in response to an acquisition end instruction, generating a video digest according to the key frame.

Abstract: The present disclosure relates to a phase-locked loop circuit and a signal processing device.