Abstract: A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Abstract: Provided in the embodiments of the present application are a brightness measurement method and apparatus, a control method and apparatus for a photographic apparatus, and a medium. In the brightness measurement method, a brightness measurement circuit is used to perform brightness measurement, the brightness measurement circuit comprising: a photosensitive diode, a switch and at least two measurement groups.

Abstract: Embodiments of this application disclose a heat sink, a heat dissipation unit, and a server. A first surface of the heat sink is provided with a heat dissipation fin, and a second surface of the heat sink is configured to dock with a circuit board. A heating element, such as a chip, is arranged on the circuit board. A die of the chip is located on a surface of the chip away from the circuit board, that is, the chip is packaged into a flipchip or packaged into a flipchip with an exposed die. At a position corresponding to the die, the second surface of the heat sink is provided with a protection groove, with a cross-sectional area of the protection groove being at least greater than an area of the die.

Abstract: This disclosure relates to a method, an apparatus, and a data processing device for controlling a frequency search speed, the method for controlling the frequency search speed including: obtaining parameter information of a frequency search speed regulation gear; obtaining a frequency search parameter based on the parameter information of the frequency search speed regulation gear; and performing frequency search based on the obtained frequency search parameter.

Abstract: The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Abstract: The present disclosure is directed to a series-connected power supply circuit and a data processing device. The series-connected power supply circuit comprises: at least two layers of to-be-powered chips (A1, A2, . . . , Am) connected in series between a first power supply end (A) and a second power supply end (B), with a highest-layer to-be-powered chip (Am) in the at least two layers of to-be-powered chips (A1, A2, . . . , Am) connected to the first power supply end (A), and a bottommost-layer to-be-powered chip (A1) in the at least two layers of to-be-powered chips (A1, A2, . . . , Am) connected to the second power supply end (B); and each layer of auxiliary power supply units (B1, B2, . . . , Bm), which is respectively connected to each layer of the to-be-powered chips (A1, A2, . . . , Am), wherein the first power supply end (A) is configured to receive a reference voltage.

Abstract: A D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

Abstract: A method, an apparatus, a blockchain server and a storage medium for determining a temperature of a cooling liquid are provided. The method includes: determining a first average temperature of a plurality of chips and a first average power of the plurality of chips in a blockchain server, in which the blockchain server includes a liquid cooling system, the liquid cooling system includes a liquid cooling plate and the plurality of chips, the plurality of chips and the liquid cooling plate are in exchange of heat, and the cooling liquid is contained in the liquid cooling plate; determining a thermal resistance coefficient of the liquid cooling system; and determining a first temperature of the cooling liquid based on the first average temperature, the first average power and the thermal resistance coefficient.

Abstract: An electronic device includes an arithmetic unit layer and a power supply. The arithmetic unit layer comprises at least one arithmetic unit. Each arithmetic unit comprises a first housing in a shape of cuboid. A first side direction of the first housing extends in a first direction. The first housing is provided with first and second openings at both ends in the first side direction thereof to form a coolant passage extending in the first direction. The power supply is stacked with arithmetic unit layer in a second or a third direction. A first side direction of the power supply is aligned with the first side direction of each arithmetic unit. The power supply is provided with third and fourth openings at both ends in the first side direction thereof to form a coolant passage extending in the first side direction of the power supply.

Abstract: The present disclosure relates to a circuit unit, a logic circuit, a processor, and a computing apparatus. A circuit unit is provided, including: an output terminal (OUT); an output stage (105), configured to provide an output signal to the output terminal; a first node (A), to which an input of the output stage is connected; and a feedback stage (107) that receives the output signal at the output terminal and selectively provides feedback to the node. A logic circuit is further provided, including an input stage that receives a signal input, and the circuit unit. The first node receives a signal based on an output of the input stage.

Abstract: This application discloses a liquid cooling heat dissipation plate and a liquid cooling electronic device, wherein the liquid cooling heat dissipation plate includes a cooling plate unit, a liquid inlet and a liquid outlet are provided at side walls of the cooling plate unit, the liquid inlet is in connection with the liquid outlet through a penetrating channel, and the penetrating channel respectively penetrates two opposite mounting surfaces of the cooling plate unit; further, a pair of fin bases are respectively lapped at positions on the two mounting surfaces corresponding to the same straight channel, and the seal plate unit is lapped at a position on the mounting surface corresponding to positions in the penetrating channel that are not covered by the fin base; and any two of the fin base, the seal plate unit, and the mounting surface are fastened by friction welding.

Abstract: The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Abstract: Embodiments of the present disclosure provide a voice wake-up method, apparatus, electronic device, and readable storage medium. The method includes: acquiring a deep feature encoded by a voice activity detection (VAD) encoding layer through a VAD decoding layer, the deep feature being extracted from a digital audio signal used for VAD encoding and voice wake-up encoding; determining whether each audio segment in the digital audio signal is a voice according to a probability that each audio frame in the digital audio signal is a voice frame, each audio segment including a plurality of audio frames; and when determining that the audio segment is the voice, indicating, by the VAD decoding layer, to input a deep feature of the audio segment into a voice wake-up decoding layer to perform voice wake-up. The embodiments of the present disclosure improve the accuracy of voice wake-up.

Abstract: Embodiments of this application provide a chip frequency control method and apparatus, a blockchain server, and a storage medium. The method includes: determining a real-time computing power ratio of a chip of a blockchain server, a real-time temperature of the chip, and a real-time voltage of the chip; and adjusting a setting frequency of the chip based on a first comparison result of the real-time computing power ratio with a reference computing power ratio of the chip, a second comparison result of the real-time temperature with a reference temperature of the chip, and a third comparison result of the real-time voltage with a reference voltage of the chip, wherein the reference computing power ratio, the reference temperature, and the reference voltage are determined when the blockchain server undergoes a frequency rising phase after start-up and enters a working status. When an exception occurs in the chip, timely and appropriate response can improve stability of the blockchain server.

Abstract: Disclosed is a method for determining configuration parameters of a data processing device, including: operating the data processing device by using configuration parameters, which are universal optimization configuration parameters obtained according to a universal operating parameter model; during the operating process, changing the configuration parameters to obtain a dedicated operating parameter data set, which includes a plurality of groups of operating parameters, each of which includes configuration parameters and capability parameters of the data processing device when the data processing device is operating under the configuration parameters; executing model training by using the dedicated operating parameter data set to obtain a dedicated operating parameter model; and obtaining optimal configuration parameters according to the dedicated operating parameter model, and operating the data processing device according to the optimal configuration parameters, where the optimal configuration parameters a

Abstract: The present disclosure relates to an apparatus and a method for a real-time clock (RTC) module of a system-on-chip (SoC), and provides an apparatus for powering battery-powered RTC module of an SoC. The apparatus is integrated in the RTC module and comprises: a first regulator stage comprising one or more regulators, wherein the first regulator stage is configured to provide a core power supply voltage (VDD_CORE) on the basis of battery output voltage (VDD_BAT); and a crystal oscillator I/O unit, the crystal oscillator I/O unit being powered by the core power supply voltage (VDD_CORE) and an I/O power supply voltage (VDD_IO), wherein the apparatus directly provides the battery output voltage (VDD_BAT) as the I/O power supply voltage (VDD_IO).

Abstract: Disclosed in embodiments of the present application are a liquid-cooling heat dissipation apparatus, a liquid-cooling data processing device and a temperature equalization method. The liquid-cooling heat dissipation apparatus includes a housing unit and a first liquid-cooling plate arranged in the housing unit. A first electronic unit and a second electronic unit are arranged on a first cooling surface and a second cooling surface arranged oppositely of the first liquid-cooling plate respectively, and the first electronic unit and the second electronic unit may be, for example, hashboards, that is, in the liquid-cooling heat dissipation apparatus provided in the embodiment of the present application, one liquid-cooling plate is correspondingly provided with two hashboards.

Abstract: This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.

Abstract: A data processing device and a data processing system are provided. The data processing device includes a housing, which is thermally conductive and defines a sealed accommodating cavity; a hashboard, which is arranged in the accommodating cavity and is in fixed connection to the housing; a control board, which is in communicative connection to the hashboard; and a power supply module, which is in electrical connection to the hashboard.

Abstract: A memory management method for a device, and a memory management device and a computing system.